- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359677 > MT90883A (Zarlink Semiconductor Inc.) TDM to Packet Processors PDF資料下載
參數(shù)資料
| 型號： | MT90883A |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | TDM to Packet Processors |
| 中文描述： | TDM到分組處理器 |
| 文件頁數(shù)： | 79/97頁 |
| 文件大?。?/td> | 702K |
| 代理商： | MT90883A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁當前第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁
MT90880/1/2/3
Data Sheet
79
Zarlink Semiconductor Inc.
Free-run Mode is typically used when a master clock source is required, or immediately following system
power-up before network synchronization is achieved.
6.13.4 DPLL Performance Parameters
Table 30 lists the key performance parameters of the DPLL.
Table 30 - DPLL Performance Parameters
Note 1:
For the DPLL, the intrinsic output jitter is determined by the frequency of the master clock input (S_CLK). The edges of the
DPLL output clocks are synchronous to both edges of the master clock, giving a resolution of 7.6 ns for a 66 MHz clock. In
addition, any jitter present on the master clock is transferred without attenuation to the output clocks.
Note that the locking range is related to the master clock frequency (S_CLK). For example, if the master clock is -100 ppm,
the whole locking range also shifts -100 ppm downwards from -345ppm to 145ppm.
Assumes ideal master clock (S_CLK) frequency of 66.0 MHz. Any deviation of master clock frequency from 66 MHz directly
translates into a degradation of free-run frequency accuracy.
This is equivalent to 7ns per 125
μ
s, or better than specified in GR-1244-CORE (reference 10) which states that the phase
slope may not exceed 81 ns/1.327 ms (61 ppm).
Assumes no drift on the master clock (S_CLK) frequency. Any drift in master clock frequency after holdover is entered will
translate directly into a holdover frequency error.
Maximum jitter is 1 UI (1 bit period) of input clock frequency. With input clock frequencies of 2.048 MHz and 4.096 MHz, this
comfortably exceeds ITU-T standards G.823 and G.824 (references 11 and 12). With a 16.384 MHz input clock, this translates
to 61 ns, or 0.125 UI at 2.048 MHz. This is just outside the G.823 specification of 0.2 UI.
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
7.0 Memory Map and Register definitions
Details of the memory map and register definitions are included in the document "MT90880 Programmers'
Model" (related document 1).
8.0 Special Note to Users: MT9088x handling of received corrupted Ethernet packets
and dealing with the next valid packet
8.1 Issue
Whenever the MT9088x device receives Ethernet packets which are corrupted (CRC error, too short or too long
etc.) the context related to the error packet will have incorrect data. The next valid packet following the error packet
will be lost and this may belong to a different context.
Parameter
Min
Max
Units
Comment
Intrinsic jitter
±
3.8
ns
Note 1
Lock range
±
245
ppm
Note 2
Lock time
50
s
Free-run frequency accuracy
±
0.005
ppm
Note 3
Master Mode Parameters
(the following parameters are only applicable in master mode):
Phase slope output
56
ppm
Note 4
Holdover frequency accuracy
±
0.06
ppm
Note 5
MTIE during a reference switch
20
ns
Slave Mode Parameters
(the following parameters are only applicable in slave mode):
Input clock jitter tolerance (above 10 KHz)
1
UI
Note 6
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90883IG | TDM to Packet Processors |
| MT9088IG | TDM to Packet Processors |
| MT8960 | Integrated PCM Filter Codec |
| MT8963AE1 | Integrated PCM Filter Codec |
| MAQ2901CL | Circular Connector; No. of Contacts:85; Series:; Body Material:Aluminum Alloy; Connecting Termination:Solder; Connector Shell Size:40; Circular Contact Gender:Socket; Circular Shell Style:Wall Mount Receptacle RoHS Compliant: No |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90883A/IG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90883BP1N | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90883IG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT9088IG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT9092 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO2-CMOS ST-BUS⑩ FAMILY Digital Telephone with HDLC (HPhone-II) |
發(fā)布緊急采購，3分鐘左右您將得到回復。