參數(shù)資料
型號(hào)： MT90883A
廠商： Zarlink Semiconductor Inc.
英文描述： TDM to Packet Processors
中文描述： TDM到分組處理器
文件頁數(shù)： 63/97頁
文件大小： 702K
代理商： MT90883A
MT90880/1/2/3
Data Sheet
63
Zarlink Semiconductor Inc.
Fields from Packet Engine Control Register:
Table 28 - Control Register Fields for Example Traffic Class 4
6.9 Memory Management Unit
The Memory Management Unit handles all access to the external packet memory, arbitrating between the
different modules requiring access. Efficient use of external memory is maintained by allocating memory in
small blocks or “granules”.
Features include:
Interfaces to industry standard PBSRAM and ZBT SSRAM
Operates at 66 MHz
32 bit wide data path
Supports one to four equal sized memory banks
Supports a total of between 0.125 and 8 Mbytes of memory
Identification
Mask
Flags
Mask
Fragment Offset
Mask
Time to Live (TTL)
Mask
Protocol
Allow Match
0d6 (TCP)
Header Checksum
Mask
Source IP address
Mask
Destination IP address
Allow Match
Check the packet has the right IP address for CPU
control traffic.
Remainder of the header
Mask
Control Register Field
Value
Comment
CPU_SEL4
set to 0b1
Send packets to the CPU.
CPU_PRI4
set to 0b11
Send to queue 3.
Byte offset to Context Descriptor
Don't care
Not TDM traffic
Protocol Field
Mask
Match / Comment
Table 27 - Pattern Matching for Example Traffic Class 4 (continued)
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