參數(shù)資料
型號(hào)： MT90882BP1N
廠(chǎng)商： Zarlink Semiconductor Inc.
英文描述： TDM to Packet Processors
中文描述： TDM到分組處理器
文件頁(yè)數(shù)： 93/97頁(yè)
文件大?。?/td> 702K
代理商： MT90882BP1N
MT90880/1/2/3
Data Sheet
93
Zarlink Semiconductor Inc.
10.5 System Control Port
Table 38 - System Clock
Note 1:
The System clock frequency stability affects the holdover-operating mode of the DPLL. Holdover Mode is typically used for
short durations while network synchronisation is temporarily disrupted. Drift on the system clock directly affects the Holdover
Mode accuracy. Note that the absolute system clock accuracy does not affect the Holdover accuracy, only the change in the
system clock (S_CLK) accuracy while in Holdover. For example, if the system clock oscillator has a temperature coefficient of
0.1 ppm/
0
C, a 10
0
C change in temperature while the DPLL is in the Holdover Mode will result in a frequency accuracy offset
of 1 ppm. The intrinsic frequency accuracy of the DPLL Holdover Mode is 0.06 ppm, excluding the system clock drift.
The system clock frequency affects the operation of the DPLL in free-run mode. In this mode, the DPLL provides timing and
synchronisation signals which are based on the frequency of the master clock (S_CLK) only. The free-run frequency accuracy
of the DPLL is
±
0.005 ppm plus the accuracy of the master clock (i.e. frequency of clock output C8OB equals 8.192 MHz
±
S_CLK_accuracy
±
0.005 ppm).
The absolute S_CLK accuracy must be controlled to
±
32 ppm in synchronous mode to enable the internal DPLL to function
correctly.
In asynchronous mode the DPLL is not used. Therefore the tolerance on S_CLK may be relaxed slightly.
Note 2:
Note 3:
Note 4:
10.6 JTAG Interface
Table 39 - JTAG Interface
Note 1:
Note 2:
Note 3:
TRST is an asynchronous signal. The setup time is for test purposes only
Non Test (other than TDI and TMS) signal input timing with respect to TCLK
Non Test (other than TDO) signal output timing with respect to TCLK
Parameter
Symbol
Min.
Typ.
Max.
Units
Notes
System Clock Frequency
CLK
FR
66
MHz
Notes 1 and 2
System
Clock
Accuracy
(synchronous mode)
CLK
ACS
±
32
ppm
Note 3
System Clock Accuracy
(asynchronous mode)
CLK
ACA
±
200
ppm
Note 4
Parameter
Symbol
Min.
Typ.
Max.
Units
Notes
TCK Frequency of Operation
0
10
25
MHz
TCK Cycle time
t
CYC
40
-
ns
TCK Clock pulse width
t
LOW
, t
HIGH
20
-
ns
TCK rise and fall time
0
3
ns
TRST Setup time to TCK falling edge
t
RSTSU
10
-
ns
Note 1
TRST Assert time
t
RST
10
-
ns
Input data setup time
t
JSU
5
-
ns
Note 2
Input data hold time
t
JH
15
-
ns
Note 2
TCK to Output data valid
t
JDV
0
30
ns
Note 3
TCK to Output data high impedance
t
JZ
0
30
ns
Note 3
TMS, TDI Data setup time
t
TPSU
5
-
ns
TMS, TDI Data hold time
t
TPH
15
-
ns
TCK to TDO data valid
t
TPODV
0
15
ns
TCK to TDO High impedance
t
TPZ
0
15
ns
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MT90883BP1N 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
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