參數(shù)資料
型號(hào): MT90882BP1N
廠商: Zarlink Semiconductor Inc.
英文描述: TDM to Packet Processors
中文描述: TDM到分組處理器
文件頁(yè)數(shù): 31/97頁(yè)
文件大小: 702K
代理商: MT90882BP1N
MT90880/1/2/3
Data Sheet
31
Zarlink Semiconductor Inc.
Packet Interface to WAN Access Interface
Incoming data is received by the MAC, and its destination address is checked. Packets intended for this device
are passed to the packet receive block for placing in external memory, while the header is classified to
determine the appropriate destination. A pointer to the packet is passed to the queue manager to be placed on
the correct queue as indicated by the classification result. The WAN Transmit block retrieves the data from
packet memory, and directs it towards the appropriate timeslots on the WAN interface.
Figure 12 - Packet to WAN Data Flow
W
Host Interface
Local TDM
Interface
Data Flow
Control Flow
P
Packet Memory
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90882IG 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT90883 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT90883A 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT90883A/IG 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT90883BP1N 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors