- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359234 > MT90820 (Zarlink Semiconductor Inc.) Large Digital Switch PDF資料下載
參數(shù)資料
| 型號： | MT90820 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Large Digital Switch |
| 中文描述： | 大型數(shù)字開關(guān) |
| 文件頁數(shù)： | 8/37頁 |
| 文件大?。?/td> | 573K |
| 代理商： | MT90820 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁
MT90820
Data Sheet
8
Zarlink Semiconductor Inc.
Wide Frame Pulse (WFP) Frame Alignment Timing
When the device is in WFP frame alignment mode, the CLK input must be at 16.384 MHz, the FE/HCLK input is
4.096 MHz and the 8 kHz frame pulse is in ST-BUS format. The timing relationship between CLK, HCLK and the
frame pulse is defined in Figure 12.
When WFPS pin is high, the frame alignment evaluation feature is disabled, but the frame input offset registers may
still be programmed to compensate for the varying frame delays on the serial input streams.
Switching Configurations
The MT90820 maximum non-blocking switching configurations is determined by the data rates selected for the
serial inputs and outputs. The switching configuration is selected by two DR bits in the IMS register. See Table 8
and Table 9.
2.048 Mb/s Serial Links (DR0=0, DR1=0)
When the 2.048 Mb/s data rate is selected, the device is configured with 16-input/16-output data streams each
having 32 64 Kbit/s channels each. This mode requires a CLK of 4.094 MHz and allows a maximum non-blocking
capacity of 512 x 512 channels.
4.096 Mb/s Serial Links (DR0=1, DR1=0)
When the 4.096 Mb/s data rate is selected, the device is configured with 16-input/16-output data streams each
having 64 64 Kbit/s channels each. This mode requires a CLK of 8.192 MHz and allows a maximum non-blocking
capacity of 1,024 x 1,024 channels.
8.192 Mb/s Serial Links (DR0=0, DR1=1)
When the 8.192 Mb/s data rate is selected, the device is configured with 16-input/16-output data streams each
having 128 64 Kbit/s channels each. This mode requires a CLK of 16.384 MHz and allows a maximum non-
blocking capacity of 2,048 x 2,048 channels. Table 1 summarizes the switching configurations and the relationship
between different serial data rates and the master clock frequencies.
Table 1 - Switching Configuration
Serial Interface
Data Rate
Master Clock
Required
(MHz)
Matrix Channel
Capacity
2 Mb/s
4.096
512 x 512
4 Mb/s
8.192
1,024 x 1,024
8 Mb/s
16.384
2,048 x 2,048
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90820AL | Large Digital Switch |
| MT90820AL1 | Large Digital Switch |
| MT90823AL1 | 3V Large Digital Switch |
| MT90823 | 3V Large Digital Switch |
| MT90823AB | 3V Large Digital Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90820AL | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K/1K X 1K/512 X 512 131.072MBPS 5V 100MQFP - Trays |
| MT90820AL1 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K/1K X 1K/512 X 512 131.072MBPS 5V 100MQFP - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH 2048X2048 100MQFP 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH 2048X2048 100MQFP |
| MT90820AP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Large Digital Switch |
| MT90820AP1 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Large Digital Switch |
| MT90820APR | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K/1K X 1K/512 X 512 5V 84PLCC - Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。