參數(shù)資料
型號(hào): MT90820
廠商: Zarlink Semiconductor Inc.
英文描述: Large Digital Switch
中文描述: 大型數(shù)字開關(guān)
文件頁數(shù): 33/37頁
文件大?。?/td> 573K
代理商: MT90820
MT90820
Data Sheet
33
Zarlink Semiconductor Inc.
Figure 16 - Multiplexed Bus Timing (Mode2)
Note 1:
High Impedance is measured by pulling to the appropriate rail with R
L
, with timing corrected to cancel time taken to discharge
C
L
.
AC Electrical Characteristics
- Motorola Non-Multiplexed Bus Mode
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
2
3
4
CS setup from DS falling
R/W setup from DS falling
Address setup from DS falling
CS hold after DS rising
R/W hold after DS rising
Address hold after DS rising
Data setup from DTA Low on Read
Data hold on read
t
CSS
t
RWS
t
ADS
t
CSH
t
RWH
t
ADH
t
DDR
t
DHR
0
ns
ns
ns
ns
ns
ns
ns
ns
10
2
0
5
5
0
10
5
6
7
C
L
=150pF
C
L
=150pF, R
L
=1K
Note 1
8
50
75
9
Data setup on write (fast write)
Valid Data Delay on write (slow write)
t
DSW
t
SWD
t
DHW
t
AKD
20
ns
ns
ns
10
122
11
12
Data hold on write
Acknowledgment Delay:
Reading/Writing Registers
Reading/Writing Memory, @ 2Mb/s
@ 4Mb/s
@ 8Mb/s
Acknowledgment Hold Time
8
55/60
760/780
400/420
220/240
80
ns
ns
ns
ns
ns
C
L
=150pF
C
L
=150pF
C
L
=150pF
C
L
=150pF
C
L
=150pF, R
L
=1K,
Note 1
13
t
AKH
45
V
TT
V
TT
DS
R/W
AS
AD0-AD7
D8-D15
AD0-AD7
D8-D15
DTA
t
RWS
t
AKD
t
ASW
t
DSH
t
RWH
t
ADS
t
ADH
t
DWS
t
DHW
t
CSS
t
DHR
t
CSH
CS
t
DDR
t
AKH
WR
RD
t
SW
V
TT
HiZ
HiZ
ADDRESS
DATA
HiZ
HiZ
ADDRESS
V
TT
V
TT
V
TT
V
TT
DATA
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MT90820AP 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Large Digital Switch
MT90820AP1 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Large Digital Switch
MT90820APR 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K/1K X 1K/512 X 512 5V 84PLCC - Tape and Reel