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參數(shù)資料
| 型號： | MT9079 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Advanced Controller for E1(先進的E1幀調節(jié)器和控制器) |
| 中文描述： | 高級控制器素E1（先進的素E1幀調節(jié)器和控制器） |
| 文件頁數(shù)： | 43/60頁 |
| 文件大?。?/td> | 347K |
| 代理商： | MT9079 |
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MT9079
4-249
Common Channel Signalling Interface
Figure 14 shows how to interface DSTi and DSTo
time slot 16 to the MC68302 for the control of
Common Channel Signalling (CCS) data. As can be
seen in the timing diagram, the MT8980D CSTo
signal must be programmed to go high during the bit
position just before time slot 16 (i.e., time slot 15, bit
0). This will enable the NMSI1 pins for one time slot
(eight C2 cycles) when the NMSI1 port is operated in
PCM mode. The STo stream of the MT8980D must
also be programmed to be high impedance during
time slot 16. C2 is used to clock data into and out of
the NMSI1 port.
It should be noted that the DS signal of the MC68302
must be inverted to interface to the MT8980D. Also,
DTACK must be connected to the MT8980D DTA and
pulled-up with a 909 ohms resistor.
G.703 and G.704 Operation
The MT9079 supports three basic G.703 2.048
Mbit/sec. configurations. The first is normal framing
where receive G.703 data is clocked onto the
ST-BUS based on addresses which are referenced to
the receive G.704 Frame Alignment Signal (FAS). On
the transmit side the ST-BUS channel zero (and
optionally channel 16) are replaced by G.704 framer
generated signals. The second is transparent mode,
which is described in the next application section.
The third configuration is where the MT9079 passes
G.703 data on to another framing device such as an
HDLC controller. That is, the receive data is clocked
onto the ST-BUS without any reference to a G.704
FAS and transmit data is not altered by the framer.
This is described in Table 67. In this configuration the
control and status functions that are associated with
individual channels will not work predictably. Other
functions such as HDB3 encoding, interrupts,
loopbacks, RSLIP, LOSS, AISS, AUXP and the BPV
error counter work normally. The control bits CRCM,
MODE and RxG704 are cleared by either a software
or hardware reset.
The MT9079 Transparent Mode
Figure 15 illustrates an application in which the
MT9079 transparent mode can be used. That is, a
digital cross-connect multiplexer that switches
complete PCM 30 trunks and does not require time
slot switching. It should be noted that any MT9079
devices that transport time slot switched data must
operate in termination mode otherwise, the CRC-4
remainder will be in error.
In transparent mode the complete PCM 30 data
stream will pass through the MT9079 except for the
data link (S
a4
of the NFAS - 4kbit/sec. maintenance
channel). The CRC-4 remainder will not be
generated by the transmit section of the MT9079, but
the CRC-4 remainder bits received on DSTi will be
modified to reflect the new data link bits. This has the
advantage that any CRC-4 errors that occur on the
receive span will not be masked on the transmit span
even though the maintenance channel has been
modified. See Table 67.
The RxMF signal must be associated with the CRC-4
multiframe (control bit MFSEL = 1), and RxMF of the
receive trunk must be connected to TxMF of the
transmit trunk. The data delay time (DSTo to DSTi)
and the TxMF to RxMF delay must be equal.
Therefore, a m + 1 frame delay circuit is added to the
TxMF to RxMF connection (where: m is the delay in
basic frames through the Digital Cross-Connect
Matrix).
It should be noted that in the TxMF to RxMF
operation is only valid when the C4i/C2i input of
MT9079 devices is driven by a C4 clock signal.
Table 67 - 2.048 Mbit/sec. Interface Configurations
Function
CRCM
MODE
G.704
Normal Framing Mode
. Both the transmit and receive sides of the
MT9079 perform normal E1 G.704 framing functions. One of the Sa4 -
Sa8 control bits must be selected for the DL pin interface to function.
0
0
0
Transparent Mode
. DSTo data is aligned with the receive FAS. DSTi data
passes through the transmit side of the MT9079 with only the Sa4 data
altered by the DL pin interface. The CRC-4 remainder is modified (not
recalculated) to reflect the altered Sa4 bit. If CRCM is low, Sa4 data is not
altered by the DL pin interface.
1
1
0
G.703 Framing Mode
. Receive G.703 data passes through the MT9079
onto DSTo without any G.704 frame alignment. Transmit data passes
through the MT9079 without being altered. CRCM must be low or the
transmit DL interface bits will be unpredictably inserted into the G.703
transmit data.
0
1
1
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT9079AC | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS ST-BUS? FAMILY Advanced Controller for E1 |
| MT9079AE | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS ST-BUS? FAMILY Advanced Controller for E1 |
| MT9079AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS ST-BUS⑩ FAMILY Advanced Controller for E1 |
| MT9079AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS ST-BUS⑩ FAMILY Advanced Controller for E1 |
| MT9079APR | 制造商:Microsemi Corporation 功能描述:FRAMER E1 5V 44PLCC - Tape and Reel |
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