參數(shù)資料
型號(hào): MT9079
廠商: Mitel Networks Corporation
英文描述: Advanced Controller for E1(先進(jìn)的E1幀調(diào)節(jié)器和控制器)
中文描述: 高級(jí)控制器素E1(先進(jìn)的素E1幀調(diào)節(jié)器和控制器)
文件頁數(shù): 30/60頁
文件大?。?/td> 347K
代理商: MT9079
MT9079
4-236
Bit
Name
Functional Description
7
EBI
(0)
Receive
unmasked an interrupt is initiated
when a receive E-bit indicates a
remote CRC-4 error. 1 - unmasked, 0
-
masked.
Interrupt
00100000.
E-bit
Interrupt.
When
vector
=
6
CRCI
(0)
CRC-4
unmasked an interrupt is initiated
when a local CRC-4 error occurs. 1 -
unmasked, 0 - masked. Interrupt vec-
tor = 00100000.
Error
Interrupt.
When
5
CEFI
(0)
Consecutively Errored FASs Inter-
rupt. When unmasked an interrupt is
initiated
when
errored frame alignment signals are
received. 1 - unmasked, 0 - masked.
Interrupt vector = 00100000.
two
consecutive
4
BPVI
(0)
Bipolar Violation Interrupt. When
unmasked an interrupt is initiated
when a bipolar violation error occurs.
1 - unmasked, 0 - masked. Interrupt
vector = 00100000.
3
RCRI
(0)
RAI and Continuous CRC Error Inter-
rupt. When unmasked an interrupt is
initiated when the RAI and continu-
ous CRC error counter is incre-
mented. 1 - unmasked, 0 - masked.
Interrupt vector = 00100000.
2
BERI
(0)
Bit Error Interrupt. When unmasked
an interrupt is initiated when a bit
error occurs. 1 - unmasked, 0 -
masked.
Interrupt
00100000.
vector
=
1
---
Unused.
0
SIGI
(0)
Signalling (CAS) Interrupt. When
unmasked and any of the receive
ABCD bits of any channel changes
state an interrupt is initiated. 1 -
unmasked, 0 - masked. Interrupt vec-
tor = 00000001
Table 37 - Interrupt Mask Word One
(Page 1, Address 1CH)
Bit
Name
Functional Description
7
EBO
(0)
Receive E-bit Counter Overflow
Interrupt. When unmasked an inter-
rupt is initiated when the E-bit error
counter changes form FFH to 0H. 1 -
unmasked, 0 - masked. Interrupt vec-
tor = 00010000.
6
CRCO
(0)
CRC-4 Error Counter Overflow Inter-
rupt. When unmasked an interrupt is
initiated when the CRC-4 error
counter changes form FFH to 0H. 1 -
unmasked, 0 - masked. Interrupt vec-
tor = 00010000.
5
CALNI
(0)
CRC-4 Alignment Interrupt. When
unmasked an interrupt is initiated
when the CALN status bit of page 3,
address 12H changes state. 1 -
unmasked, 0 - masked. Interrupt vec-
tor = 00001000.
4
FERO
(0)
Frame
Counter Overflow Interrupt. When
unmasked an interrupt is initiated
when the frame alignment signal
error counter changes form FFH to
0H. 1 - unmasked, 0 - masked. Inter-
rupt vector = 00010000.
Alignment
Signal
Error
3
RCRO
(0)
RAI and Continuous CRC-4 Error
Counter Overflow Interrupt. When
unmasked an interrupt is initiated
when the RAI and Continuous error
counter changes form FFH to 0H. 1 -
unmasked, 0 - masked. Interrupt vec-
tor = 00010000.
2
BERO
(0)
Bit Error Counter Overflow Interrupt.
When unmasked an interrupt is initi-
ated when the bit error counter
changes form FFH to 0H. 1 -
unmasked, 0 - masked. Interrupt vec-
tor = 00010000.
1
AUXPI
(0)
Auxiliary Pattern Interrupt. When
unmasked an interrupt is initiated
when the AUXP status bit of page 3,
address 15H goes high. 1 -
unmasked, 0 - masked. Interrupt vec-
tor = 01000000.
0
---
Unused.
Table 38 - Interrupt Mask Word Two
(Page 1, Address 1DH)
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