
MT9079
4-240
Status Page 3
Tables 51 to 58 describe the bit functions of the page
3 status registers.
Bit
Name
Functional Description
7
SYNC
Receive Basic Frame Alignment.
Indicates the basic frame alignment
status (1 - loss; 0 - acquired).
6
MFSYNC
Receive Multiframe Alignment. Indi-
cates the multiframe alignment status
(1 - loss; 0 -acquired).
5
CRCSYN
Receive
Indicates the CRC-4 multiframe
alignment status (1 - loss; 0 -
acquired).
CRC-4
Synchronization.
4
REB1
Receive E-Bit One Status. This bit
indicates the status of the received
E1 bit of the last multiframe.
3
REB2
Receive E-Bit Two Status. This bit
indicates the status of the received
E2 bit of the last multiframe.
2
CRCRF
CRC-4 Reframe. A one indicates that
the receive CRC-4 multiframe syn-
chronization could not be found
within the time out period of 8 msec.
after detecting basic frame synchro-
nization. This bit is cleared when
CRC-4 synchronization is achieved.
1
PSYNC
Synchronization Persistence. This bit
will go high when the SYNC status bit
goes high (loss of basic frame align-
ment). It will persist high for eight
msec. after SYNC has returned low,
and then return low.
0
CRCIWK
CRC-4 Interworking. This bit indi-
cates the CRC-4 interworking status
(1 - CRC-to-CRC;
0 - CRC-to-non-CRC).
Table 51 - Synchronization Status Word
(Page 3, Address 10H)
Bit
Name
Functional Description
7
RIU0
Receive International Use Zero. This
is the bit which is received on the
PCM 30 2048 kbit/sec. link in bit
position one of the frame alignment
signal. It is used for the CRC-4
remainder or for international use.
6 - 0
RFA2-8
Receive Frame Alignment Signal Bits
2 to 8. These bit are received on the
PCM 30 2048 kbit/sec. link in bit
positions two to eight of frame align-
ment signal. These bits form the
frame alignment signal and should
be 0011011.
Table 52 - Receive Frame Alignment Signal
(Page 3, Address 11H)
Bit
Name
Functional Description
7
1SEC
One Second Timer Status. This bit
changes state once every 0.5 sec-
onds and is synchronous with the
2SEC timer.
6
2SEC
Two Second Timer Status. This bit
changes state once every second
and is synchronous with the 1SEC
timer.
5
CRCT
CRC-4
changes from one-to-zero at the start
of the one second interval in which
CRC errors are accumulated. This bit
stays high for 8 msec.
Timer
Status.
This
bit
4
EBT
E-Bit Timer Status. This bit changes
from one-to-zero at the start of the
one second interval in which E-bit
errors are accumulated. This bit
stays high for 8 msec.
3
400T
400 msec. Timer Status. This bit
changes state when the 400 msec.
CRC-4 multiframe alignment timer
expires.
2
8T
8 msec. Timer Status. This bit
changes state when the 8 msec.
CRC-4 multiframe alignment timer
expires.
1
CALN
CRC-4 Alignment. When CRC-4 mul-
tiframe alignment has not been
achieved this bit changes state every
2 msec. When CRC-4 multiframe
alignment has been achieved this bit
is synchronous with the receive
CRC-4 multiframe signal.
0
---
Unused.
Table 53 - Timer Status Word
(Page 3, Address 12H)