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MT9072
Data Sheet
115
Zarlink Semiconductor Inc.
17.1.2 Interrupt Mask Registers Address (Y40-Y4F) Summary
17.1.3 Master Control Registers (Y00 to YF0 ) Bit Functions
Tables 64 to 79 describe the bit functions of each of the Master Control Registers in the MT9072. Each register is
repeated for each of the 8 framers. Framer 0 is addressed with Y=0, Framer 1 with Y=1, Framer 2 with Y=2,...
Framer 7 with Y=7 (where Y represents the 4 most significant address bits (MSB) A
11
A
10
A
9
A
8
). In addition, a
simultaneous write to all 8 Framers is possible by setting the address A11 to 1 and A10 to A8 to 0. A (0), (1) or (#)
in the “Name” column of these tables indicates the state of the data bits after a hard reset (the RESET pin is toggled
from zero to one), or a software reset (the RST bit in control register address YF1 is toggled from one to zero or
toggling of RSTC in Global Control Register). The (#) indicates that a (0) or (1) is possible.
Binary Address
(A11-A0)
AHex
Interrupt Mask
Register
Control Bits
(B15 - B8 / B7 - B0)
yyyy 0010 0000-
yyyy 0010 0010
Y40-Y42
-
not used
not used
yyyy 0100 0011
Y43
R
HDLC Interrupt Mask
#,#,#,#,#,#,#,GAIM,EOPDIM,TEOPIM,EOPRIM,
TXFLIM,FAIM,TXUNDERIM,RXFFIM,RXOVFLIM
yyyy 0100 0100
Y44
R
Receive Sync and
Alarm Interrupt Mask
FEOIM,CRCOIM,OOFOIM,COFAOIM,BPVOIM,
PRBSOIM,PRBSMFOIM,MFOOFOIM,TFSYNIM,
MFSYNIM,FBEIM,COFAIM,SEFIM,AISIM,CRCIM,
LOSIM
yyyy 0100 0101
Y45
R
Receive Line status
and Timer Interrupt
Mask
D4YALMIM,D4Y48IM,SECYELIM,ESFYELIM,
T1DMYIM,#,BPVIM,PRBSIM,PDVIM,LLEDIM,
LLDDIM,BIOMIM,BOMMIM,CASRIM,1SECIM,2SE
CIM
yyyy 0100 0110
Y46
R
Elastic Store and
Excessive Zero
Interrupt Mask
#,#,#,#,#,#,#,#,#,#,#,EXZOIM,EXZIM,TXSLIPIM,
RXSLIPIM
yyyy 0100 0111
yyyy 0100 1111
Y47-Y4F
R
not used
not used
xxxx indicates all (0000 to 1111) binary possibilities
X indicates all (0 to F) hex possibilities
yyyy indicates 9 (000, 001, 010, 011, 111,1000,1001) binary possibilities representing 1 of 8 framers (R/W), and
all 8 framers (W only) and global selection.
Y indicates 9 (0,1,2,3,4...9) hex possibilities representing 1 of 8 framers (R/W), and all 8 framers (W only) and
global selection.
Table 62 - Interrupt Mask Register (R/W) Address (Y4X) Summary (T1)