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參數(shù)資料
| 型號(hào)： | MT90221 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad IMA/UNI PHY Device |
| 中文描述： | 四IMA的/單向物理層設(shè)備 |
| 文件頁數(shù)： | 82/114頁 |
| 文件大?。?/td> | 304K |
| 代理商： | MT90221 |
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MT90221
74
Address (Hex):
Direct access
Reset Value (Hex):
204
00
Bit #
Type
Description
7:4
3:0
R
Unused. Should read 0’s.
Each bit set to ’1’ will enable the generation of the interrupt when the corresponding bit in
the IRQ IMA Group Overflow Status register is set. There is one bit for each status bit.
R/W
Table 99 - IRQ IMA Group Overflow Enable Register
Address (Hex):
Direct access
210 - 213
1 register per IMA Group. The RxClk and TxClk signals must be active for correct
register operation
00
Reset Value (Hex):
Bit #
Type
Description
7:5
4
R
Unused. Should read 0’s.
This bit is set when the RX UTOPIA FIFO associated with an IMA Group overflows. This
bit is cleared by writing 0.
This bit is set when the counter for all cells associated with an IMA Group overflows.
(Input UTOPIA port). This bit is cleared by writing 0.
This bit is set when the counter for Idle Cells associated with an IMA Group overflows.
(Input UTOPIA port). This bit is cleared by writing 0.
This bit is set when the counter for Unassigned Cells associated with an IMA Group
overflows. (Input UTOPIA port). This bit is cleared by writing 0.
This bit is set when the counter for HEC Errored Cells associated with an IMA Group
overflows. (Input UTOPIA port). This bit is cleared by writing 0.
R/W
3
R/W
2
R/W
1
R/W
0
R/W
Table 100 - IRQ IMA Overflow Status Registers
Address (Hex):
Direct access
register operation
Reset Value (Hex):
208 - 20B
1 register per link. The RxClk and TxClk signals must be active for correct
00
Bit #
Type
Description
7:5
4
R
Unused. Should read 0’s.
This bit is set when the RX UTOPIA FIFO associated with a Link in UNI mode overflows.
This bit is cleared by writing 0.
This bit is set when the UTOPIA Input counter for all cells (or all Stuff cells event)
associated with a link used in UNI mode overflows. This bit is cleared by writing 0.
This bit is set when the UTOPIA Input counter for Idle Cells associated with a link used in
UNI mode overflows. This bit is cleared by writing 0.
This bit is set when the UTOPIA Input counter for Unassigned Cells associated with a link
used in UNI mode overflows. This bit is cleared by writing 0.
This bit is set when the UTOPIA Input counter for HEC Errored Cells associated with a
link used in UNI mode overflows. This bit is cleared by writing 0.
R/W
3
R/W
2
R/W
1
R/W
0
R/W
Table 101 - IRQ UTOPIA UNI Overflow Status Registers
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90221AL | Quad IMA/UNI PHY Device |
| MT9041B | T1/E1 System Synchronizer |
| MT9041BP | T1/E1 System Synchronizer |
| MT9041 | Multiple Output Trunk PLL |
| MT9041AP | IC REG LDO 150MA 5.0V 0.5% 8SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90221AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device |
| MT90222 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:4/8/16 Port IMA/TC PHY Device |
| MT90222AG | 制造商:Microsemi Corporation 功能描述:ATM IMA 40MBPS 2.5V 384BGA - Trays |
| MT90222AG2 | 制造商:Microsemi Corporation 功能描述:ATM IMA 40MBPS 2.5V 384BGA /BAKE/DRYPACK - Trays |
| MT90223AG | 制造商:Microsemi Corporation 功能描述:ATM IMA 80MBPS 2.5V 384BGA - Trays |
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