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256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65
–
Rev. E; Pub. 3/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
256Mb: x4, x8, x16
SDRAM
SINGLE WRITE – WITHOUT AUTO PRECHARGE
1
TIMING PARAMETERS
-7E
-75
SYMBOL*
t
AH
t
AS
t
CH
t
CL
t
CK (3)
t
CK (2)
t
CKH
t
CKS
t
CMH
MIN
0.8
1.5
2.5
2.5
7
7.5
0.8
1.5
0.8
MAX
MIN
0.8
1.5
2.5
2.5
7.5
10
0.8
1.5
0.8
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CMS
t
DH
t
DS
t
RAS
t
RC
t
RCD
t
RP
t
WR
1.5
0.8
1.5
37
60
15
15
14
1.5
0.8
1.5
44
66
20
20
15
ns
ns
ns
ns
ns
ns
ns
ns
120,000
120,000
*CAS latency indicated in parentheses.
DISABLE AUTO PRECHARGE
ALL BANKS
tCH
tCL
tCK
tRP
tRAS
tRC
tRCD
DQM /
DQML, DQMU
CKE
CLK
A0-A9, A11
DQ
BA0, BA1
A10
tCMH
tCMS
tAH
tAS
ROW
BANK
BANK
BANK
ROW
ROW
BANK
tWR
D
IN
m
tDH
tDS
COMMAND
tCMH
tCMS
NOP
4
NOP
4
PRECHARGE
ACTIVE
NOP
WRITE
ACTIVE
NOP
NOP
tAH
tAS
tAH
tAS
SINGLE BANK
tCKH
tCKS
COLUMN
m
3
2
T0
T1
T2
T4
T3
T5
T6
T7
T8
DON
’
T CARE
-7E
-75
SYMBOL*
MIN
MAX
MIN
MAX
UNITS
NOTE:
1. For this example, the burst length = 1, and the WRITE burst is followed by a
“
manual
”
PRECHARGE.
2. 14ns to 15ns is required between <D
IN
m
> and the PRECHARGE command, regardless of frequency. With a single write
tWR has been increased to meet minimum tRAS requirement.
3. x16: A8, A9, and A11 =
“
Don
’
t Care
”
x8: A9 and A11 =
“
Don
’
t Care
”
x4: A11 =
“
Don
’
t Care
”
4. PRECHARGE command not allowed else
t
RAS would be violated.