參數(shù)資料
型號(hào)： MT48LC32M8A2
廠(chǎng)商： Micron Technology, Inc.
英文描述： SYNCHRONOUS DRAM
中文描述： 同步DRAM
文件頁(yè)數(shù)： 20/62頁(yè)
文件大?。?/td> 1517K
代理商： MT48LC32M8A2
20
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65
–
Rev. E; Pub. 3/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
256Mb: x4, x8, x16
SDRAM
This is shown in Figure 7 for CAS latencies of two and
three; data element
n
+ 3 is either the last of a burst of
four or the last desired of a longer burst. The 256Mb
SDRAM uses a pipelined architecture and therefore
does not require the 2
n
rule associated with a prefetch
Figure 7
Consecutive READ Bursts
architecture. A READ command can be initiated on any
clock cycle following a previous READ command. Full-
speed random read accesses can be performed to the
same bank, as shown in Figure 8, or each subsequent
READ may be performed to a different bank.
DON
’
T CARE
NOTE:
Each READ command may be to any bank. DQM is LOW.
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
BANK,
COL
n
NOP
BANK,
COL
b
D
OUT
n
+ 1
D
OUT
n
+ 2
D
OUT
n
+ 3
D
OUT
b
READ
X = 1 cycle
CAS Latency = 2
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
BANK,
COL
n
NOP
BANK,
COL
b
D
OUT
n
+ 1
D
OUT
n
+ 2
D
OUT
n
+ 3
D
OUT
b
READ
NOP
T7
X = 2 cycles
CAS Latency = 3
相關(guān)PDF資料
PDF描述
MT48LC16M16A2 SYNCHRONOUS DRAM
MT48LC64M4A2 SYNCHRONOUS DRAM
MT48LC4M32B2 SYNCHRONOUS DRAM
MT48LC4M32LFFC SYNCHRONOUS DRAM
MT48LC64M8A2 SYNCHRONOUS DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT48LC32M8A2-75 制造商:Micron Technology Inc 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*