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256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65
–
Rev. E; Pub. 3/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
256Mb: x4, x8, x16
SDRAM
NOTE:
1. Violating refresh requirements during power-down may result in a loss of data.
POWER-DOWN MODE
1
tCH
tCL
tCK
Two clock cycles
CKE
CLK
DQ
All banks idle, enter
power-down mode
Precharge all
active banks
Input buffers gated off while in
power-down mode
Exit power-down mode
(
)
(
)
(
)
(
)
DON
’
T CARE
tCKS
tCKS
COMMAND
tCMH
tCMS
PRECHARGE
NOP
NOP
ACTIVE
NOP
(
)
(
)
(
)
(
)
All banks idle
BA0, BA1
BANK
BANK(S)
(
)
(
)
(
)
(
)
High-Z
tAH
tAS
tCKH
tCKS
DQM/
DQML, DQMU
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
A0-A9, A11, A12
ROW
(
)
(
)
(
)
(
)
ALL BANKS
SINGLE BANK
A10
ROW
(
)
(
)
(
)
(
)
T0
T1
T2
Tn + 1
Tn + 2
*CAS latency indicated in parentheses.
-7E
-75
SYMBOL*
t
CK (2)
t
CKH
t
CKS
t
CMH
t
CMS
MIN
7.5
0.8
1.5
0.8
1.5
MAX
MIN
10
0.8
1.5
0.8
1.5
MAX
UNITS
ns
ns
ns
ns
ns
TIMING PARAMETERS
-7E
-75
SYMBOL*
t
AH
t
AS
t
CH
t
CL
t
CK (3)
MIN
0.8
1.5
2.5
2.5
7
MAX
MIN
0.8
1.5
2.5
2.5
7.5
MAX
UNITS
ns
ns
ns
ns
ns