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Table 11: AC Operating Specifications and Conditions (Continued)
Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;
VDDQ = +1.5–1.9V, VDD = +1.5–1.9V
AC Characteristics
-25E
-25
-3E
-3
-37E
Units
Notes
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Command
and
Address
Input setup time
tISb
175
–
175
–
200
–
200
–
250
–
ps
Input hold time
tIHb
250
–
250
–
275
–
275
–
375
–
ps
Input setup time
tISa
375
–
375
–
400
–
400
–
500
–
ps
Input hold time
tIHa
375
–
375
–
400
–
400
–
500
–
ps
Input pulse width
tIPW
0.6
–
0.6
–
0.6
–
0.6
–
0.6
–
tCK
ACTIVATE-to- ACTIVATE
delay, same bank
tRC
55
–
55
–
54
–
55
–
55
–
ns
ACTIVATE-to-READ or
WRITE delay
tRCD
12.5
–
15
–
12
–
15
–
15
–
ns
ACTIVATE-to- PRE-
CHARGE delay
tRAS
40
70K
40
70K
40
70K
40
70K
40
70K
ns
PRECHARGE period
tRP
12.5
–
15
–
12
–
15
–
15
–
ns
PRECHARGE
ALL period
<1Gb
tRPA
12.5
–
15
–
12
–
15
–
15
–
ns
≥1Gb
tRPA
15
–
17.5
15
18
18.75
ns
ACTIVATE -to-
ACTIVATE
delay differ-
ent bank
x4, x8
tRRD
7.5
–
7.5
–
7.5
–
7.5
–
7.5
–
ns
x16
tRRD
10
–
10
–
10
–
10
–
10
–
ns
4-bank
activate
period
(
≥1Gb)
x4, x8
tFAW
35
–
35
–
37.5
–
37.5
–
37.5
–
ns
x16
tFAW
45
–
45
–
50
–
50
–
50
–
ns
Internal READ-to-PRE-
CHARGE delay
tRTP
7.5
–
7.5
–
7.5
–
7.5
–
7.5
–
ns
CAS#-to-CAS# delay
tCCD
2
–
2
–
2
–
2
–
2
–
tCK
Write recovery time
tWR
15
–
15
–
15
–
15
–
15
–
ns
Write AP recovery + pre-
charge time
tDAL
tWR +
tRP
–
tWR +
tRP
–
tWR +
tRP
–
tWR +
tRP
–
tWR +
tRP
–
ns
Internal WRITE-to-READ
delay
tWTR
7.5
–
7.5
–
7.5
–
7.5
–
7.5
–
ns
LOAD MODE cycle time
tMRD
2
–
2
–
2
–
2
–
2
–
tCK
1Gb:
x4,
x8,
x16
1.55V
DDR2
SDRAM
AC
Timing
Operating
Specifications
PDF:
09005aef82b91d01
1GbDDR2_1_55V.PDF
Rev.
A
5/09
EN
32
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Technology,
Inc.
reserves
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right
to
change
products
or
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without
notice.
2009
Micron
Technology,
Inc.
All
rights
reserved.