參數(shù)資料
型號(hào): MT47H64M16HR-3IT
元件分類: DRAM
英文描述: 64M X 16 DDR DRAM, 0.4 ns, PBGA84
封裝: 8 X 12.50 MM, ROHS COMPLIANT, FBGA-84
文件頁(yè)數(shù): 54/129頁(yè)
文件大?。?/td> 9252K
代理商: MT47H64M16HR-3IT
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)當(dāng)前第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)
Table 11: AC Operating Specifications and Conditions (Continued)
Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;
VDDQ = +1.5–1.9V, VDD = +1.5–1.9V
AC Characteristics
-25E
-25
-3E
-3
-37E
Units
Notes
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Data
Strobe-Out
DQS output access time
from CK/CK#
tDQSCK
–350
+350
–350
+350
–400
+400
–400
+400
–450
+450
ps
DQS read preamble
tRPRE
MIN = 0.9 × tCK
MAX = 1.1 × tCK
tCK
DQS read postamble
tRPST
MIN = 0.4 × tCK
MAX = 0.6 × tCK
tCK
CK/CK# to DQS
Low-Z
tLZ1
MIN = tAC (MIN)
MAX = tAC (MAX)
ps
Data
Strobe-In
DQS rising edge to CK
rising edge
tDQSS
MIN = –0.25 × tCK
MAX = +0.25 × tCK
tCK
DQS input-high pulse
width
tDQSH
MIN = 0.35 × tCK
MAX = n/a
tCK
DQS input-low pulse
width
tDQSL
MIN = 0.35 × tCK
MAX = n/a
tCK
DQS falling to CK
rising: setup time
tDSS
MIN = 0.2 × tCK
MAX = n/a
tCK
DQS falling from CK
rising: hold time
tDSH
MIN = 0.2 × tCK
MAX = n/a
tCK
Write preamble setup
time
tWPRES
MIN = 0
MAX = n/a
ps
DQS write preamble
tWPRE
MIN = 0.35 × tCK
MAX = n/a
tCK
DQS write postamble
tWPST
MIN = 0.4 × tCK
MAX = 0.6 × tCK
tCK
WRITE command to first
DQS transition
MIN = WL - tDQSS
MAX = WL + tDQSS
tCK
1Gb:
x4,
x8,
x16
1.55V
DDR2
SDRAM
AC
Timing
Operating
Specifications
PDF:
09005aef82b91d01
1GbDDR2_1_55V.PDF
Rev.
A
5/09
EN
30
Micron
Technology,
Inc.
reserves
the
right
to
change
products
or
specifications
without
notice.
2009
Micron
Technology,
Inc.
All
rights
reserved.
相關(guān)PDF資料
PDF描述
MT48H8M16LFB4-8IT:JTR 8M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54
MT48LC4M32TG-10 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO54
MT48V8M16LFB4-8XT 8M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54
MT48LC4M32LFB5-10ES:G 4M X 32 SYNCHRONOUS DRAM, 7 ns, PBGA90
MT48V4M32TG-8XT 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO54
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT47H64M16HR-3L 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM