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參數(shù)資料
| 型號(hào)： | MT28F160S3 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 2 Meg x 8/1 Meg x 16 Smart 3 Flash(2 M x 8/1 M x 16閃速存儲(chǔ)器) |
| 中文描述： | 2梅格× 8 /檢測起× 16智能3閃光（2 M中的x 8月1日M中的x 16閃速存儲(chǔ)器） |
| 文件頁數(shù)： | 28/39頁 |
| 文件大小： | 281K |
| 代理商： | MT28F160S3 |
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28
2 Meg x 8 /1 Meg x 16 Even-Sectored Flash Memory
MT28F160S3_2 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2 MEG x 8/1 MEG x 16
SMART 3 EVEN-SECTORED FLASH
PRELIMINARY
DESIGN CONSIDERATIONS
THREE-LINE OUTPUT CONTROL
This device has three control inputs to provide
multiple memory connections: CE0#, CE1#, and
OE#. Three-line control affords (1) lowest possible
memory power dissipation; and (2) data bus conten-
tion avoidance.
To use these control inputs optimally, an address
decoder should enable CEx#, while OE# should be
connected to all memory devices and the system’s
READ# control line. This ensures that only selected
memory devices have active outputs, while deselected
memory devices are in standby mode. RP# should be
connected to the system POWERGOOD signal to pre-
vent unintended WRITEs during system power transi-
tions. POWERGOOD should also toggle during system
reset.
STS AND ISM POLLING
The open drain output pin STS should be connected
to V
CC
by a pull-up resistor to provide a hardware form
of detecting block erase, program, and lock bit configu-
ration completion. In default mode, it transitions LOW
during execution of these commands and returns to
V
OH
when the ISM has finished executing the internal
algorithm. See STS Configuration Command section
for alternate STS configurations. STS can be connected
to an interrupt input of the system CPU or controller.
STS is active at all times. In the default mode, STS is also
V
OH
during block erase suspend or reset/power-down.
POWER SUPPLY DECOUPLING
Flash memory power switching characteristics re-
quire careful device decoupling. Active current levels,
standby current levels, and transient peaks produced by
falling and rising edges of CEx# and OE# are areas of
consideration. Two-line control and proper decoupling
capacitor selection can suppress transient voltage peaks.
Each device should have a 0.1μF ceramic capacitor
connected between its V
CC
and GND and V
PP
and GND.
These high-frequency, low-inductance capacitors
should be placed as close as possible to package leads.
In addition, for every eight devices, a 4.7μF electrolytic
capacitor should be placed at the array’s power supply
connection between V
CC
and GND. The bulk capacitor
will overcome voltage slumps caused by PC board trace
inductance.
V
CC
, V
PP
, RP# TRANSITIONS
If RP#
≤
V
IH
, or if V
PP
or V
CC
fall outside of a valid
voltage range (V
CC
1/2
and V
PPH
1/2/3
), block erase, pro-
gram, and lock bit configuration are not guaranteed.
If V
PP
error is detected, status register bits SR3 and SR4
or SR5 are set to “1.” If RP# transitions to V
IL
during
block erase, program, or lock bit configuration, STS in
RY/BY# level mode will remain LOW until the RESET
operation is complete. Then, the operation will abort
and the device will enter deep power-down. Because the
aborted operation may leave data partially altered, the
command sequence must be repeated after normal
operation is restored.
POWER-UP/DOWN PROTECTION
This device provides protection against accidental
block erase, programming, or lock bit configuration
during power transitions.
System designers must guard against spurious writes
for V
CC
voltages above V
LKO
when V
PP
is active. Since
both WE# and CEx# must be LOW for a command
write, driving either input signal to V
IH
will inhibit
WRITEs. The CEL’s two-step command sequence archi-
tecture provides an added level of protection against
data alteration. In-system block lock and unlock pro-
vides additional protection during power-up by pro-
hibiting BLOCK ERASE and PROGRAM operations.
RP# = V
IL
disables the device, regardless of its control
inputs states.
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