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參數(shù)資料
| 型號： | MSM82C37B-5GS-2K |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | DMA控制器 |
| 英文描述： | 4 CHANNEL(S), 5 MHz, DMA CONTROLLER, PQFP44 |
| 封裝： | 9 X 10 MM, 0.80 MM PITCH, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 7/34頁 |
| 文件大?。?/td> | 327K |
| 代理商： | MSM82C37B-5GS-2K |
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Semiconductor
MSM82C37B-5RS/GS/VJS
OUTLINE OF FUNCTIONS
The MSM82C37B-5 consists of five blocks = three logic sections, an internal register section, and
a counter section.
The logic sections include a timing control block where the internal timing and external control
signals are generated, a command control block where each instruction from the CPU is
decoded, and a priority decision block where the order of DMA channel priority is determined.
The purpose of the internal register section is to hold internal states and instructions from the
CPU, while the counter section computes addresses and word counts.
DESCRIPTION OF OPERATIONS
The MSM82C37B-5 operates in two cycles (called the idle and active cycles) which are divided
into independent states. Each state is commenced by a clock falling edge and continues for a
single clock cycle. The transition from one state to the next in DMA operations is outlined in
Figure 1.
Idle Cycle
The idle cycle is entered from the Sl state when there is no valid DMA request on any
MSM82C37B-5 channel. During this cycle, DREQ and CS inputs are monitored during each
cycle. When a valid DMA request is then received, an active cycle is commenced. And if the
HLDA and CS inputs are at low level, a programming state is started with MSM82C37B-5
reading or writing executed by IOR or IOW. Programming details are described later.
Active Cycle
If a DMA request is received in an unmasked channel while the MSM82C37B-5 is in idle cycle,
or if a software DREQ is generated, the HRQ is changed to high level to commence an active
cycle. The initial state of an active cycle is the S0 state which is repeated until the HLDA input
from the CPU is changed to high level. (But because of internal operational reasons, a minimum
of one clock cycle is required for the HLDA is be changed to high level by the CPU after the HRQ
has become high level. That is, the S0 state must be repeated at least twice.)
After the HLDA has been changed to high level, the S0 state proceeds to operational states S1
thru S4 during I/O-memory transfers, or to operational states S11 thru S14 and S21 thru S24
during memory-memory transfers.
If the memory or I/O device cannot be accessed within the normal timing, an SW state (wait
state) can be inserted by a READY input to extend the timing.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSM82C37B-5RS | 4 CHANNEL(S), 5 MHz, DMA CONTROLLER, PDIP40 |
| MSM82C37B-5GS-2K | 4 CHANNEL(S), 5 MHz, DMA CONTROLLER, PQFP44 |
| MSM82C43GS-K | 20 I/O, PIA-GENERAL PURPOSE, PDSO24 |
| MSM82C51A-2GS | 1 CHANNEL(S), 64K bps, SERIAL COMM CONTROLLER, PDSO32 |
| MSM82C54-2GS-K | 3 TIMER(S), PROGRAMMABLE TIMER, PDSO32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSM82C37B-5JS | 制造商:OK International 功能描述:4 CHANNEL(S), 5 MHZ, DMA CONTROLLER, PQCC44 |
| MSM82C37B-5RS | 制造商:OK International 功能描述:4 CHANNEL(S), 5 MHz, DMA CONTROLLER, PDIP40 |
| MSM82C37B-5VJS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:PROGRAMMABLE DMA CONTROLLER |
| MSM82C43 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:INPUT/OUTPUT PORT EXPANDER |
| MSM82C51A-2GS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER |
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