參數(shù)資料
型號： MSM82C37B-5GS-2K
廠商： OKI ELECTRIC INDUSTRY CO LTD
元件分類： DMA控制器
英文描述： 4 CHANNEL(S), 5 MHz, DMA CONTROLLER, PQFP44
封裝： 9 X 10 MM, 0.80 MM PITCH, PLASTIC, QFP-44
文件頁數(shù)： 5/34頁
文件大小： 327K
代理商： MSM82C37B-5GS-2K
13/33
Semiconductor
MSM82C37B-5RS/GS/VJS
Symbol
Pin Name
Input/Output
Function
End of Process
EOP
Input/Output
EOP is active-low bidirectional three-state signal. Unlike other
pins, this pin is an N-channel open drain. During DMA operations,
a low-level output pulse is obtained from this pin if the channel
word count changes from 0000H to FFFFH.
And DMA transfers can be terminated by pulling the EOP input to
low level. Both of these actions are called terminal count (TC).
Hold Request
HRQ
Output
HRQ is active-high signal used as an output of hold request to
the CPU for system data bus control purposes. After HRQ has
become active, at least one clock cycle is required before HLDA
becomes active.
Address Enable
AEN
Output
AEN is active-high ouput signal used to indicate that output
signals sent from the MSM82C37B-5 to the system are valid.
And in addition to enabling external latch to hold the eight higher
order bits of the transfer address, this signal is also used to
disable other system bus buffers.
DMA Acknowledge
0 - 3 Channels
DACK0 -
DACK3
Output
DACK is output signals used to indicate that DMA transfer to
peripheral devices has been permitted. (Available in each channel.)
Although these pins are switched to active-low when reset, they
can be programmed to become active-high.
Address 0 - 3
A0 - A3
Input/Output
A0 - A3 is bidirectional three-state signals used as input signals
for specifying the MSM82C37B-5 internal register to be accessed
by the CPU during idle cycles, and as an output the four lower
order bits of the transfer address during active cycles.
Address 4 - 7
A4 - A7
Output
A4 - A7 is three-state signals used as an output the four higher
order bits of the transfer address during active cycles.
Note that there is no DACK output signal during memory-memory
transfers.
When internal or external EOP is generated, the MSM82C37B-5
terminates the transfer and resets the DMA request.
When the EOP pin is not used, it is necessary to hold the pin at
high level by pull-up resistor to prevent the input of an EOP
by error. Also note that the EOP function cannot be satisfied in
cascade mode.
Memory Read
MEMR
Output
MEMR is active-low three-state output signal used as a control
signal in reading data from memory during read transfers and
memory-memory transfers.
Memory Write
MEMW
Output
MEMW is active-low three-state output signal used as a control
signal in writing data into memory during write transfers and
memory-memory transfers.
Address Strobe
ADSTB
Output
ADSTB is active-high signal used to strobe the eight higher order
bits of the transfer address by external latch.
PIN FUNCTIONS (continued)
相關(guān)PDF資料
PDF描述
MSM82C37B-5RS 4 CHANNEL(S), 5 MHz, DMA CONTROLLER, PDIP40
MSM82C37B-5GS-2K 4 CHANNEL(S), 5 MHz, DMA CONTROLLER, PQFP44
MSM82C43GS-K 20 I/O, PIA-GENERAL PURPOSE, PDSO24
MSM82C51A-2GS 1 CHANNEL(S), 64K bps, SERIAL COMM CONTROLLER, PDSO32
MSM82C54-2GS-K 3 TIMER(S), PROGRAMMABLE TIMER, PDSO32
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MSM82C37B-5JS 制造商:OK International 功能描述:4 CHANNEL(S), 5 MHZ, DMA CONTROLLER, PQCC44
MSM82C37B-5RS 制造商:OK International 功能描述:4 CHANNEL(S), 5 MHz, DMA CONTROLLER, PDIP40
MSM82C37B-5VJS 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:PROGRAMMABLE DMA CONTROLLER
MSM82C43 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:INPUT/OUTPUT PORT EXPANDER
MSM82C51A-2GS 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER
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