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參數(shù)資料
| 型號(hào)： | MSM82C37B-5GS-2K |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | DMA控制器 |
| 英文描述： | 4 CHANNEL(S), 5 MHz, DMA CONTROLLER, PQFP44 |
| 封裝： | 9 X 10 MM, 0.80 MM PITCH, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 13/34頁 |
| 文件大?。?/td> | 327K |
| 代理商： | MSM82C37B-5GS-2K |
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Semiconductor
MSM82C37B-5RS/GS/VJS
Fixed Priority Mode
In fixed priority mode, channel 0 has the highest priority, followed by channels 1, 2, and 3 in that
order.
Rotating Priority Mode
In rotating priority mode, the order of priority is changed so that the channel where the current
DMA transfer has been completed is given lowest priority. This is to prevent any one channel
from monopolizing the system.
The fixed priority is regained immediately after resetting.
Service Terminated Channel
—
CH0
Priority Mode
Fixed
CH1
Order of Priority
for Next DMA
CH2
CH3
Highest
Lowest
CH1
CH2
Rotating
CH3
CH0
CH1
CH3
CH0
CH1
CH2
CH3
CH2
CH3
CH0
CH1
CH2
CH0
CH1
CH2
CH3
CH0
Table 1 MSM82C37B-5 Priority Decision Modes
Compressed Timing
Setting the MSM82C37B-5 to compressed timing mode enables the S3 state used in extension of
the read pulse access time to be omitted (if permitted by system structure) for two or three clock
cycle DMA transfers. If the S3 state is omitted, the read pulse width becomes the same as the
write pulse width with the address updated in S2 and the read or write operation executed in
S4. This mode is disregarded if the transfer is a memory-memory transfer, transfer.
Extended Writing
When this mode is set, the IOW or MEMW signal which normally appears during the S3 state
is obtained during the S2 state, thereby extending the write pulse width. The purpose of this
extended write pulse is to enable the system to accomodate memories and I/O devices where
the access time is slower. Although the pulse width can also be extended by using READY, that
involves the insertion of a SW state to increase the number of states.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSM82C37B-5RS | 4 CHANNEL(S), 5 MHz, DMA CONTROLLER, PDIP40 |
| MSM82C37B-5GS-2K | 4 CHANNEL(S), 5 MHz, DMA CONTROLLER, PQFP44 |
| MSM82C43GS-K | 20 I/O, PIA-GENERAL PURPOSE, PDSO24 |
| MSM82C51A-2GS | 1 CHANNEL(S), 64K bps, SERIAL COMM CONTROLLER, PDSO32 |
| MSM82C54-2GS-K | 3 TIMER(S), PROGRAMMABLE TIMER, PDSO32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSM82C37B-5JS | 制造商:OK International 功能描述:4 CHANNEL(S), 5 MHZ, DMA CONTROLLER, PQCC44 |
| MSM82C37B-5RS | 制造商:OK International 功能描述:4 CHANNEL(S), 5 MHz, DMA CONTROLLER, PDIP40 |
| MSM82C37B-5VJS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:PROGRAMMABLE DMA CONTROLLER |
| MSM82C43 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:INPUT/OUTPUT PORT EXPANDER |
| MSM82C51A-2GS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER |
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