Each power supply pin (
參數(shù)資料
型號(hào)： MSC7119VM1200
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 43/60頁(yè)
文件大?。?/td> 0K
描述： DSP 16BIT W/DDR CTRLR 400-MAPBGA
標(biāo)準(zhǔn)包裝： 90
系列： StarCore
類型： 定點(diǎn)
接口： 主機(jī)接口，I²C，UART
時(shí)鐘速率： 300MHz
非易失內(nèi)存： ROM（8 kB）
芯片上RAM： 464kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 400-LFBGA
供應(yīng)商設(shè)備封裝： 400-MAPBGA（17x17）
包裝： 托盤
MSC7119 Data Sheet, Rev. 8
Hardware Design Considerations
Freescale Semiconductor
48
3.2.3
Power Planes
Each power supply pin (VDDC, VDDM, and VDDIO) should have a low-impedance path to the board power supply. Each GND pin
should be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on the device.
The MSC7119 VDDC power supply pins should be bypassed to ground using decoupling capacitors. The capacitor leads and
associated printed circuit traces connecting to device power pins and GND should be kept to less than half an inch per capacitor
lead. A minimum four-layer board that employs two inner layers as power and GND planes is recommended. See Section 3.5
for DDR Controller power guidelines.
3.2.4
Decoupling
Both the I/O voltage and core voltage should be decoupled for switching noise. For I/O decoupling, use standard capacitor
values of 0.01
μF for every two to three voltage pins. For core voltage decoupling, use two levels of decoupling. The first level
should consist of a 0.01 F high frequency capacitor with low effective series resistance (ESR) and effective series inductance
(ESL) for every two to three voltage pins. The second decoupling level should consist of two bulk/tantalum decoupling
capacitors, one 10
μF and one 47 μF, (with low ESR and ESL) mounted as closely as possible to the MSC7119 voltage pins.
Additionally, the maximum drop between the power supply and the DSP device should be 15 mV at 1 A.
3.2.5
PLL Power Supply Filtering
The MSC7119 VDDPLL power signal provides power to the clock generation PLL. To ensure stability of the internal clock, the
power supplied to this pin should be filtered with capacitors that have low and high frequency filtering characteristics. VDDPLL
can be connected to VDDC through a 2 Ω resistor. VSSPLL can be tied directly to the GND plane. A circuit similar to the one
shown in Figure 35 is recommended. The PLL loop filter should be placed as closely as possible to the VDDPLL pin (which are
located on the outside edge of the silicon package) to minimize noise coupled from nearby circuits.The 0.01 F capacitor should
be closest to VDDPLL, followed by the 0.1 F capacitor, the 10 F capacitor, and finally the 2-Ω resistor to VDDC. These traces
should be kept short.
3.2.6
Power Consumption
You can reduce power consumption in your design by controlling the power consumption of the following regions of the device:
Extended core. Use the SC1400 Stop and Wait modes by issuing a stop or wait instruction.
Clock synthesis module. Disable the PLL, timer, watchdog, or DDR clocks or disable the CLKO pin.
AHB subsystem. Freeze or shut down the AHB subsystem using the GPSCTL[XBR_HRQ] bit.
Peripheral subsystem. Halt the individual on-device peripherals such as the DDR memory controller, Ethernet MAC,
HDI16, TDM, UART, I2C, and timer modules.
For details, see the “Clocks and Power Management” chapter of the MSC711x Reference Manual.
Figure 35. PLL Power Supply Filter Circuits
VDDC
VDDPLL
2
Ω
0.1 F 0.01 F
10 F
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