參數(shù)資料
型號(hào)： MPC823UM_REV1_16-CPM7
廠商： Motorola, Inc.
英文描述： 10 AMP SUBMINIATURE POWER RELAY
中文描述： 通信處理器模塊
文件頁(yè)數(shù)： 70/74頁(yè)
文件大?。?/td> 234K
代理商： MPC823UM_REV1_16-CPM7
Communication Processor Module
16-448
MPC823 REFERENCE MANUAL
MOTOROLA
S
C
1
P
DATA LENGTH
This field indicates the number of octets that the communication processor module must
transmit from this buffer descriptor data buffer. However, it is never modified by the
communication processor module. Normally, this value is greater than zero, but if the
number of data bits in the character is greater than 8, then DATA LENGTH must be even.
For example, to transmit three characters of 8-bit data, the DATA LENGTH field must be
initialized to 3. However, to transmit three characters of 9-bit data the DATA LENGTH field
must be initialized to 6, since the three 9-bit data fields occupy three half-words in memory.
The serial peripheral interface writes these bits after it finishes transmitting the associated
data buffer.
TX DATA BUFFER POINTER
This field always points to the first location of the associated data buffer. They can be even
or odd, unless the number of actual data bits in the character is greater than 8 bits, in which
case the transmit buffer pointer must be even. The buffer can reside in internal or external
memory. The serial peripheral interface writes these bits after it finishes transmitting the
associated data buffer.
16.12.4.2 SPI COMMAND REGISTER.
The 8-bit read/write SPI command (SPCOM)
register is used to start serial peripheral interface operation.
STR—Start Transmit
When the serial peripheral interface is configured as a master, setting this bit to 1 causes
the serial peripheral interface to start transmitting and receiving data to and from the
transmit/receive buffers if they are ready. When the serial peripheral interface is in slave
mode, setting the STR bit to 1 when the serial peripheral interface is idle causes the serial
peripheral interface to load the transmit data register from the SPI transmit buffer and start
transmission as soon as the next SPI input clocks and select signal are received. This bit is
automatically cleared after one system clock cycle.
Bits 1–7—Reserved.
These bits are reserved and must be set to 0.
SPCOM
BIT
0
1
2
3
4
5
6
7
FIELD
STR
RESERVED
RESET
0
0
R/W
R/W
R/W
ADDR
(IMMR & 0xFFFF0000) + 0xAAD
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