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參數(shù)資料
| 型號(hào)： | MPC823UM_REV1_16-CPM7 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 10 AMP SUBMINIATURE POWER RELAY |
| 中文描述： | 通信處理器模塊 |
| 文件頁數(shù)： | 2/74頁 |
| 文件大小： | 234K |
| 代理商： | MPC823UM_REV1_16-CPM7 |
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Communication Processor Module
16-380
MPC823 REFERENCE MANUAL
MOTOROLA
S
C
1
P
Each serial management controller supports the circuit interface and monitor channels of
the GCI bus. In which case, the serial management controller is connected to the TDM
channel in the serial interface. For testing purposes, the serial management controllers
support loopback and echo modes. The SMCx receiver and transmitter are double-buffered,
which provides an effective FIFO size (latency) of two characters. Refer to
Section 16.7 The Serial Interface with Time-Slot Assigner
the GCI interfaces.
for details about configuring
The receive data source for the two serial management controller channels have different
pin options for each channel. SMC1 can either use the L1RXDA pin of the serial interface or
the SMRXD1 pin if it is connected to the NMSI. SMC2 can also use the L1RXDA pin of the
serial interface, but if you use the SMRXD2 pin the serial interface time-slot assigner
function is not available. Likewise, the transmit data source for SMC1 can be the L1TXDA
pin if a serial management controller is connected to the TDM or the SMTXD1 pin if it is
connected to the NMSI. SMC2 transmit data source can also be L1TXDA pin if the serial
management controller is connected to the TDM, but if you use the SMTXD2 pin, the serial
interface time-slot assigner function is not available.
If the serial management controllers are connected to the TDM, the SMCx receive and
transmit clocks can be independent from each other, as defined in the CRTA bit of the
SIMODE register. Refer to
Section 16.7.5.2 Serial Interface Mode Register
information. However, if a serial management controller is connected to the NMSI, the SMCx
receive and transmit clocks must be connected to a single clock source called SMCLK,
which is an internal signal name for a clock that is generated from the bank of clocks.
SMCLK originates from an external pin or one of the two internal baud rate generators. Refer
to
Section 16.7.8 Nonmultiplexed Serial Interface Configuration
for more
for more details.
Figure 16-113. Serial Management Controller Block Diagram
CONTROL
REGISTERS
U-BUS
RX DATA
REGISTER
TX DATA
REGISTER
SHIFTER
SHIFTER
CONTROL
LOGIC
PERIPHERAL BUS
TXDx
RXDx
SYNC
CLOCK
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