參數(shù)資料
型號(hào)： MPC750
廠商： Motorola, Inc.
英文描述： Hall Effect Switch IC; Package/Case:3-SOT-23; Supply Voltage Max:24V; Current Rating:4mA; Leaded Process Compatible:Yes; Operate Point Max:90G; Operate Point Min:-90G; Operational Type:Latch; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes
中文描述： MPC750 RISC微處理器
文件頁(yè)數(shù)： 6/31頁(yè)
文件大?。?/td> 318K
代理商： MPC750
6
MPC750 RISC Microprocessor Technical Summary
For More Information On This Product,
Go to: www.freescale.com
Separate memory management units (MMUs) for instructions and data
— 52-bit virtual address; 32-bit physical address
— Address translation for 4-Kbyte pages, variable-sized blocks, and 256-Mbyte segments
— Memory programmable as write-back/write-through, cacheable/noncacheable, and coherency
enforced/coherency not enforced on a page or block basis
— Separate IBATs and DBATs (four each) also defined as SPRs
— Separate instruction and data translation lookaside buffers (TLBs)
– Both TLBs are 128-entry, two-way set associative, and use LRU replacement algorithm
– TLBs are hardware reloadable (that is, the page table search is performed in hardware)
Separate bus interface units for system memory and for the L2 cache
— Bus interface features include the following:
– Selectable bus-to-core clock frequency ratios of 2x, 2.5x, 3x, 3.5x, 4x, 4.5x ... 8x. (2x to 8x,
all half-clock multipliers in-between)
– A 64-bit, split-transaction external data bus with burst transfers
– Support for address pipelining and limited out-of-order bus transactions
– Single-entry load queue
– Single-entry instruction fetch queue
– Two-entry L1 cache castout queue
– No-DRTRY mode eliminates the DRTRY signal from the qualified bus grant. This allows
the forwarding of data during load operations to the internal core one bus cycle sooner than
if the use of DRTRY is enabled.
— L2 cache interface features (which are not implemented on the MPC740) include the following:
– Core-to-L2 frequency divisors of 1, 1.5, 2, 2.5, and 3
– Four-entry L2 cache castout queue in L2 cache BIU
– 17-bit address bus
– 64-bit data bus
Multiprocessing support features include the following:
— Hardware-enforced, three-state cache coherency protocol (MEI) for data cache.
— Load/store with reservation instruction pair for atomic memory references, semaphores, and
other multiprocessor operations
Power and thermal management
— Three static modes, doze, nap, and sleep, progressively reduce power dissipation:
– Doze—All the functional units are disabled except for the time base/decrementer registers
and the bus snooping logic.
– Nap—The nap mode further reduces power consumption by disabling bus snooping, leaving
only the time base register and the PLL in a powered state.
– Sleep—All internal functional units are disabled, after which external system logic may
disable the PLL and SYSCLK.
F
Freescale Semiconductor, Inc.
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