參數(shù)資料
型號(hào): MPC750
廠商: Motorola, Inc.
英文描述: Hall Effect Switch IC; Package/Case:3-SOT-23; Supply Voltage Max:24V; Current Rating:4mA; Leaded Process Compatible:Yes; Operate Point Max:90G; Operate Point Min:-90G; Operational Type:Latch; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes
中文描述: MPC750 RISC微處理器
文件頁(yè)數(shù): 5/31頁(yè)
文件大小: 318K
代理商: MPC750
MPC750 RISC Microprocessor Technical Summary
5
— SRU handles miscellaneous instructions
– Executes CR logical and Move to/Move from SPR instructions (
– Single-entry reservation station
Rename buffers
— Six GPR rename buffers
— Six FPR rename buffers
— Condition register buffering supports two CR writes per clock
Completion unit
— The completion unit retires an instruction from the six-entry reorder buffer (completion queue)
when all instructions ahead of it have been completed, the instruction has finished execution,
and no exceptions are pending.
— Guarantees sequential programming model (precise exception model)
— Monitors all dispatched instructions and retires them in order
— Tracks unresolved branches and flushes instructions from the mispredicted branch
— Retires as many as two instructions per clock
Separate on-chip instruction and data caches (Harvard architecture)
— 32-Kbyte, eight-way set-associative instruction and data caches
— Pseudo least-recently-used (PLRU) replacement algorithm
— 32-byte (eight-word) cache block
— Physically indexed/physical tags. (Note that the PowerPC architecture refers to physical
address space as real address space.)
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— Instruction cache can provide four instructions per clock; data cache can provide two words per
clock
— Caches can be disabled in software
— Caches can be locked in software
— Data cache coherency (MEI) maintained in hardware
— The critical double word is made available to the requesting unit when it is burst into the line-
fill buffer. The cache is nonblocking, so it can be accessed during this operation.
Level 2 (L2) cache interface (The L2 cache interface is not supported in the MPC740.)
— On-chip two-way set-associative L2 cache controller and tags
— External data SRAMs
— Support for 256-Kbyte, 512-Kbyte, and 1-Mbyte L2 caches
— 64-byte (256-Kbyte/512-Kbyte) and 128-byte (1 Mbyte) sectored line size
— Supports flow-through (register-buffer), pipelined (register-register), and pipelined late-write
(register-register) synchronous burst SRAMs
mtspr
and
mfspr
)
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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