- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382345 > MPC750 (Motorola, Inc.) Hall Effect Switch IC; Package/Case:3-SOT-23; Supply Voltage Max:24V; Current Rating:4mA; Leaded Process Compatible:Yes; Operate Point Max:90G; Operate Point Min:-90G; Operational Type:Latch; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes PDF資料下載
參數(shù)資料
| 型號： | MPC750 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Hall Effect Switch IC; Package/Case:3-SOT-23; Supply Voltage Max:24V; Current Rating:4mA; Leaded Process Compatible:Yes; Operate Point Max:90G; Operate Point Min:-90G; Operational Type:Latch; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
| 中文描述： | MPC750 RISC微處理器 |
| 文件頁數(shù)： | 16/31頁 |
| 文件大?。?/td> | 318K |
| 代理商： | MPC750 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁
16
MPC750 RISC Microprocessor Technical Summary
For More Information On This Product,
Go to: www.freescale.com
The PLL is configured by the PLL_CFG[0–3] signals, which select the multiplier that the PLL uses to
multiply the SYSCLK frequency up to the internal core frequency. The feedback in the PLL guarantees that
the processor clock is phase locked to the bus clock, regardless of process variations, temperature changes,
or parasitic capacitances. The PLL also ensures a 50% duty cycle for the processor clock.
The MPC750 supports various processor-to-bus clock frequency ratios, although not all ratios are available
for all frequencies. Configuration of the processor/bus clock ratios is displayed through a MPC750-specific
register, HID1. For information about supported clock frequencies, see the MPC750 hardware
specifications.
Part 2 MPC750 Microprocessor: Implementation
The PowerPC architecture is derived from the POWER architecture (Performance Optimized with
Enhanced RISC architecture). The PowerPC architecture shares the benefits of the POWER architecture
optimized for single-chip implementations. The PowerPC architecture design facilitates parallel instruction
execution and is scalable to take advantage of future technological gains.
This section describes the PowerPC architecture in general, and specific details about the implementation
of the MPC750 as a low-power, 32-bit member of the PowerPC processor family.
Registers and programming model—Section 2.1, “PowerPC Registers and Programming Model,”
describes the registers for the operating environment architecture common among PowerPC
processors and describes the programming model. It also describes the registers that are unique to
the MPC750.
Instruction set and addressing modes—Section 2.2, “Instruction Set,” describes the PowerPC
instruction set and addressing modes for the PowerPC operating environment architecture, and
defines and describes the PowerPC instructions implemented in the MPC750.
Cache implementation—Section 2.3, “On-Chip Cache Implementation,” describes the cache model
that is defined generally for PowerPC processors by the virtual environment architecture. It also
provides specific details about the MPC750 cache implementation.
Exception model—Section 2.4, “Exception Model,” describes the exception model of the PowerPC
operating environment architecture and the differences in the MPC750 exception model.
Memory management—Section 2.5, “Memory Management,” describes generally the conventions
for memory management among the PowerPC processors. This section also describes the
MPC750’s implementation of the 32-bit PowerPC memory management specification.
Instruction timing—Section 2.6, “Instruction Timing,” provides a general description of the
instruction timing provided by the superscalar, parallel execution supported by the PowerPC
architecture and the MPC750.
Power management—Section 2.7, “Power Management,” describes how the power management
can be used to reduce power consumption when the processor, or portions of it, are idle.
Thermal management—Section 2.8, “Thermal Management,” describes how the thermal
management unit and its associated registers (THRM1–THRM3) and exception can be used to
manage system activity in a way that prevents exceeding system and junction temperature
thresholds. This is particularly useful in high-performance portable systems, which cannot use the
same cooling mechanisms (such as fans) that control overheating in desktop systems.
Performance monitor—Section 2.9, “Performance Monitor,” describes the performance monitor
facility, which system designers can use to help bring up, debug, and optimize software
performance.
F
Freescale Semiconductor, Inc.
n
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC823 | Communication Processor Module |
| MPC823UM_REV1_16-CPM7 | 10 AMP SUBMINIATURE POWER RELAY |
| MPC9109 | LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP |
| MPC9229 | 400 MHz Low Voltage PECL Clock Synthesizer |
| MPC9230 | 800 MHz Low Voltage PECL Clock Synthesizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC75-103J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Metal Plate Cement Resistors |
| MPC75-103K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Metal Plate Cement Resistors |
| MPC75201J | 功能描述:厚膜電阻器 - 透孔 MPC7 200R 5% RoHS:否 制造商:Caddock 電阻:27 kOhms 容差:1 % 功率額定值:8 W 溫度系數(shù):50 PPM / C 系列:MS 端接類型:Axial 電壓額定值:2 kV 工作溫度范圍:- 15 C to + 275 C 尺寸:8.89 mm Dia. x 23.11 mm L 封裝:Bulk |
| MPC755 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:RISC Microprocessor Hardware Specifications |
| MPC755BPX300LE | 功能描述:微處理器 - MPU 360PBGA RV2.8 HIP4DP RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。