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參數(shù)資料
| 型號： | MPC750 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Hall Effect Switch IC; Package/Case:3-SOT-23; Supply Voltage Max:24V; Current Rating:4mA; Leaded Process Compatible:Yes; Operate Point Max:90G; Operate Point Min:-90G; Operational Type:Latch; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
| 中文描述： | MPC750 RISC微處理器 |
| 文件頁數(shù)： | 30/31頁 |
| 文件大小： | 318K |
| 代理商： | MPC750 |
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MPC750 RISC Microprocessor Technical Summary
For More Information On This Product,
Go to: www.freescale.com
The thermal management facility also ensures that the processor’s junction temperature does not exceed the
operating specification. To avoid the inaccuracies that arise from measuring junction temperature with an
external thermal sensor, the MPC750’s on-chip thermal sensor and logic tightly couples the thermal
management implementation.
The TAU consists of a thermal sensor, digital-to-analog convertor, comparator, control logic, and the
dedicated SPRs described in Section 2.1, “PowerPC Registers and Programming Model.” The TAU does the
following:
Compares the junction temperature against user-programmable thresholds
Generates a thermal management interrupt if the temperature crosses the threshold
Enables the user to estimate the junction temperature by way of a software successive
approximation routine
The TAU is controlled through the privileged
mtspr
/
mfspr
instructions to the three SPRs provided for
configuring and controlling the sensor control logic, which function as follows:
THRM1 and THRM2 provide the ability to compare the junction temperature against two user-
provided thresholds. Having dual thresholds gives the thermal management software finer control
of the junction temperature. In single threshold mode, the thermal sensor output is compared to only
one threshold in either THRM1 or THRM2.
THRM3 is used to enable the TAU and to control the comparator output sample time. The thermal
management logic manages the thermal management interrupt generation and time multiplexed
comparisons in the dual threshold mode as well as other control functions.
Instruction cache throttling provides control of the MPC750’s overall junction temperature by determining
the interval at which instructions are fetched. This feature is accessed through the ICTC register.
2.9 Performance Monitor
The MPC750 incorporates a performance monitor facility that system designers can use to help bring up,
debug, and optimize software performance. The performance monitor counts events during execution of
code, relating to dispatch, execution, completion, and memory accesses.
The performance monitor incorporates several registers that can be read and written to by supervisor-level
software. User-level versions of these registers provide read-only access for user-level applications. These
registers are described in Section 2.1, “PowerPC Registers and Programming Model.” Performance monitor
control registers, MMCR0 or MMCR1 can be used to specify which events are to be counted and the
conditions for which a performance monitoring interrupt is taken. Additionally, the sampled instruction
address register, SIA (USIA), holds the address of the first instruction to complete after the counter
overflowed.
Attempting to write to a user-read-only performance monitor register causes a program exception,
regardless of the MSR[PR] setting.
When a performance monitoring interrupt occurs, program execution continues from vector offset 0x00F00.
F
Freescale Semiconductor, Inc.
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.
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