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參數(shù)資料
| 型號(hào)： | MPC604E |
| 廠商： | Motorola, Inc. |
| 英文描述： | PowerPC 604e-TM RISC Microprocessor Technical Summary |
| 中文描述： | 的PowerPC 604e -商標(biāo)RISC微處理器技術(shù)總結(jié) |
| 文件頁數(shù)： | 7/34頁 |
| 文件大?。?/td> | 117K |
| 代理商： | MPC604E |
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PowerPC 604e RISC Microprocessor Technical Summary
7
— Caches can be locked
— Parity checking performed on both caches
— Data cache coherency (MESI) maintained in hardware
— Secondary data cache support provided
— Instruction cache coherency maintained in hardware
— Data cache line-fill buffer forwarding. In the 604 only the critical double word of the cache
block was made available to the requesting unit at the time it was burst into the line-fill buffer.
Subsequent data was unavailable until the cache block was filled. On the 604e, subsequent data
is also made available as it arrives in the line-fill buffer.
Separate memory management units (MMUs) for instructions and data
— Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte
segment size
— Both TLBs are 128-entry and two-way set associative
— TLBs are hardware reloadable (that is, the page table search is performed in hardware)
— Separate IBATs and DBATs (four each) also defined as SPRs
— Separate instruction and data translation lookaside buffers (TLBs)
— LRU replacement algorithm
— 52-bit virtual address; 32-bit physical address
Bus interface features include the following:
— Selectable processor-to-bus clock frequency ratios (1:1, 3:2, 2:1, 5:2, 3:1, and 4:1)
— A 64-bit split-transaction external data bus with burst transfers
— Support for address pipelining and limited out-of-order bus transactions
— Four burst write queues—three for cache copyback operations and one for snoop push
operations
— Two single-beat write queues
— Additional signals and signal redefinition for direct-store operations
— Provides a data streaming mode that allows consecutive burst read data transfers to occur
without intervening dead cycles. This mode also disables data retry operations.
— No-DRTRY mode eliminates the DRTRY signal from the qualified bus grant and allows read
operations. This improves performance on read operations for systems that do not use the
DRTRY signal. No-DRTRY mode makes read data available to the processor one bus clock
cycle sooner than if normal mode is used.
Multiprocessing support features include the following:
— Hardware enforced, four-state cache coherency protocol (MESI) for data cache. Bits are
provided in the instruction cache to indicate only whether a cache block is valid or invalid.
— Separate port into data cache tags for bus snooping
— Load/store with reservation instruction pair for atomic memory references, semaphores, and
other multiprocessor operations
Power management
— NAP mode supports full shut down and snooping
— Operating voltage of 2.5
±
0.3 V
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