參數(shù)資料
型號(hào)： MPC604E
廠商： Motorola, Inc.
英文描述： PowerPC 604e-TM RISC Microprocessor Technical Summary
中文描述： 的PowerPC 604e -商標(biāo)RISC微處理器技術(shù)總結(jié)
文件頁(yè)數(shù)： 28/34頁(yè)
文件大?。?/td> 117K
代理商： MPC604E
28
PowerPC 604e RISC Microprocessor Technical Summary
Asynchronous—The OEA portion of the PowerPC architecture defines two types of asynchronous
exceptions:
— Asynchronous, maskable—The PowerPC architecture defines the external interrupt and
decrementer interrupt which are maskable and asynchronous exceptions. In the 604e, and in
many PowerPC processors, the hardware interrupt is generated by the assertion of the Interrupt
(INT) signal, which is not defined by the architecture. In addition, the 604e implements one
additional interrupt, the system management interrupt, which performs similarly to the external
interrupt, and is generated by the assertion of the System Management Interrupt (SMI) signal.
When these exceptions occur, their handling is postponed until all instructions, and any
exceptions associated with those instructions, complete execution.
— Asynchronous, nonmaskable—There are two nonmaskable asynchronous exceptions that are
imprecise: system reset and machine check exceptions. Note that the OEA portion of the
PowerPC architecture, which defines how these exceptions work, does not define the causes or
the signals used to cause these exceptions. These exceptions may not be recoverable, or may
provide a limited degree of recoverability for diagnostic purpose.
The PowerPC architecture defines two bits in the machine state register (MSR)—FE0 and FE1—that
determine how floating-point exceptions are handled. There are four combinations of bit settings, of which
the 604e implements three. These are as follows:
Ignore exceptions mode (FE0 = FE1 = 0). In this mode, the instruction dispatch logic feeds the FPU
as fast as possible and the FPU uses an internal pipeline to allow overlapped execution of
instructions. In this mode, floating-point exception conditions return a predefined value instead of
causing an exception.
Precise interrupt mode (FE0 = 1; FE1 = x). This mode includes both the precise mode and imprecise
recoverable mode defined in the PowerPC architecture. In this mode, a floating-point instruction
that causes a floating-point exception brings the machine to a precise state. In doing so, the 604e
takes floating-point exceptions as defined by the PowerPC architecture.
Imprecise nonrecoverable mode (FE0 = 0; FE1 = 1). In this mode, when a floating-point instruction
causes a floating point exception, the save restore register 0 (SRR0) may point to an instruction
following the instruction that caused the exception.
The 604e exception classes are shown in Table 1.
Table 1. Exception Classifications
Type
Exception
Asynchronous/nonmaskable
Machine check
System reset
Asynchronous/maskable
External interrupt
Decrementer
System management interrupt (not defined by the PowerPC architecture)
Synchronous/precise
Instruction-caused exceptions
Synchronous/imprecise
Floating-point exceptions (imprecise nonrecoverable mode)
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