參數(shù)資料
型號(hào)： MK50H27Q25
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 1 CHANNEL(S), 51M bps, SERIAL COMM CONTROLLER, PQCC52
封裝： PLASTIC, LCC-52
文件頁(yè)數(shù)： 9/58頁(yè)
文件大?。?/td> 621K
代理商： MK50H27Q25
04
TUR
TRANSMITTER UNDERRUN indicates that the MK50H27 has aborted
a
signal unit since data was late from memory.
This condition is
reached
when the transmitter and transmitter FIFO both become
empty while transmitting a signal unit. When TUR is set, an interrupt
is generated if INEA = 1. TUR is READ/CLEAR ONLY and is set by
MK50H27 and cleared by writing a "1" into the bit. Writing a "0" has
no effect. It is also cleared by RESET or by issuing a Power Off primi-
tive.
03
PINT
PRIMITIVE INTERRUPT is set after the chip updates the primitive
register to issue a provider primitive. When PINT is set, an interrupt is
generated if INEA =1. PINT is READ/CLEAR ONLY and is set
by
MK50H27 and cleared by writing a "1" into the bit.
Writing a "0" has no
effect. It is also cleared by RESET or by issuing a Power Off primitive.
02
TINT
TRANSMITTER INTERRUPT is set after the chip updates an entry
in the Transmit Descriptor Ring. When TINT is set, an interrupt is
generated if INEA =1. TINT is READ/CLEAR ONLY and is set by
MK50H27 and cleared by writing a "1" into the bit. Writing a "0" has no
effect. It is also cleared by RESET or by issuing a PowerOff primitive.
01
RINT
RECEIVER INTERRUPT is set after the MK50H27 updates an entry in
the Receive Descriptor Ring. When RINT is set, an interrupt is gener-
ated if INEA =1. RINT is READ/CLEAR ONLY and is set by MK50H27
and cleared by writing a "1" into the bit. Writing a "0" has no effect.
It is cleared by Bus RESET or by issuing a Power Off primitive.
00
0
This bit is READ ONLY and will always read as a zero.
4.1.2.2 Control and Status Register 1 (CSR1)
RAP <3:1> = 1
BIT
NAME
DESCRIPTION
15
UERR
USER PRIMITIVE ERROR is set by the MK50H27 when a primitive is
issued by the user which is in conflict with the current status of the link.
UERR is READ/CLEAR ONLY and is set by MK50H27 and cleared by
writing a "1" into the bit. Writing a "0" in this bit has no effect. It is
also cleared by Bus RESET.
14
UAV
USER PRIMITIVE AVAILABLE is set by the user when a primitive is
written into UPRIM. It is cleared by the MK50H27 after the primitive
has been processed. This bit is also cleared by a Bus RESET.
13:08
UPRIM
USER PRIMITIVE is written by the user, in conjunction with setting
UAV, to control the MK50H27 link procedures. The following primitives
are available:
0
Power Off: causes the MK50H27 to enter the Power Off state. All DMA
activity ceases, the transmitter transmits all ones, and all
received
data is ignored. Valid in all states except Power Off.
1
Power On: valid only in the Power Off phase and must be issued after
the Init primitive and prior to the Start primitive. Causes the MK50H27
to exit the Power Off phase and to enter the Out of Service phase and
1
5
1
0
1
4
0
9
1
2
1
0
8
0
3
0
7
0
2
0
6
0
5
0
4
0
1
0
1
3
UPRIM
<5:0>
PPRIM
<5:0>
U
E
R
U
A
V
P
A
V
P
L
O
S
T
MK50H27
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