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參數(shù)資料
| 型號(hào)： | MK50H27Q25 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 51M bps, SERIAL COMM CONTROLLER, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 19/58頁 |
| 文件大?。?/td> | 621K |
| 代理商： | MK50H27Q25 |
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05
DRCK
Disable Receiver CK. When DRCK = 0, the receiver will extract
and check the CK field at the end of each signal unit. When
DRCK = 1, the receiver continues to extract the last 16 or 32 bits of
each signal unit, depending on CKS, but no check is performed to
determine whether the CK is correct. The CK is not stored into the
Receive buffer.
04
DTCK
Disable Transmitter CK. When DTCK = 0, the transmitter will
generate and append the CK to each signal unit. When DTCK = 1,
the CK logic is disabled, and no CK is generated with transmitted sig-
nal units. Setting DTCK=1 is useful in loopback testing for check-
ing the ability of the receiver to detect an incorrect CK.
03
CKS
CK Select. When CKS = 1, the 16 bit CK is selected otherwise the
32 bit CK is used.
02:00
LBACK
Loopback Control puts the MK50H27 into one of several loopback
configurations.
4.2.2 Timers
There are ten independent counter-timers defined in SS7. The upper 8 bits of IADR+02 are used
as a scaler for T1 through T7, and TP. The scaler is driven by a clock which is 1/32 of SYSCLK. N1 is
the maximum number of signal units allowed for retransmission (transmission window size) and N2 is the
maximum number of bytes allowed for retransmission. The value for N1 is set to 128.
The Host will write the period of N2, T1-T7, and TP into the Initialization Block.
TIMER
DESCRIPTION
SCALER
TIMER PRESCALER. Timers T1-T7 and TP are scaled by this
number.
The prescaler is incremented once every 32
system
clock pulses.
When it reaches zero the timers are incremented and
the prescaler is reset. This field is interpreted as the two’s comple-
ment of the prescaler period. The MK50H27 multiplies this value
by 16 when it is read into the device. Note: a prescale value of one
gives the smallest amount of scaling to the timers (512 clock pulses),
zero gives the largest (131584 clock pulses).
N2
Octet window size. N2 gives the maximum number of MSU
octets allowed for retransmission. N2 includes the opening and clos-
ing flags, BSN/BIB, FSN/FIB, LI, and the CK octets. This value is
expressed as a positive integer. Bits <14:8> of IADR + 02 represent
the most significant bits of N2.
T1
ALIGNED READY TIMER PERIOD. T1 determines the maximum
time the MK50H27 will stay in the ALIGNED READY state before sig-
nalling link failure. Represented as two’s complement.
T2
NOT ALIGNED TIMER PERIOD. T2 determines the maximum time
the MK50H27 will wait in the NOT ALIGNED state before signalling
link failure. Represented as two’s complement.
LBACK
DESCRIPTION
0
Normal operation. No loopback.
4
Simple loopback. Receive data and clock are driven internally by transmit data and clock.
Transmit clock must be supplied externally
5
Clockless loopback. Receive data is driven internally by transmit data. Transmit and receive
clocks are driven by SYSCLK divided by 8.
6
Silent loopback. Same as simple loopback with td pin forced to all ones.
7
Silent clockless loopback. Combination of Silent and Clockless loopbacks. Receive data is
driven internally by transmit data, transmit and receive clocks are driven by SYSCLK divided
by 8. The TD pin is forced to all ones.
MK50H27
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| MK50H27Q33B | 功能描述:射頻無線雜項(xiàng) SS7 Controller 33MHz RoHS:否 制造商:Texas Instruments 工作頻率:112 kHz to 205 kHz 電源電壓-最大:3.6 V 電源電壓-最小:3 V 電源電流:8 mA 最大功率耗散: 工作溫度范圍:- 40 C to + 110 C 封裝 / 箱體:VQFN-48 封裝:Reel |
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| MK50H28DIP | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:MULTI LOGICAL LINK FRAME RELAY CONTROLLER |
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