參數(shù)資料
型號(hào)： MK50H27Q25
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 1 CHANNEL(S), 51M bps, SERIAL COMM CONTROLLER, PQCC52
封裝： PLASTIC, LCC-52
文件頁(yè)數(shù)： 14/58頁(yè)
文件大?。?/td> 621K
代理商： MK50H27Q25
4.1.2.5 Control and Status Register 4 (CSR4)
CSR4 allows redefinition of the bus master interface.
RAP<3:1> = 4
BIT
NAME
DESCRIPTION
15:12
XWD0/1, RWD0/1
These bits enable and determine the timer values for the Transmit and
Receive Watchdog Timers. These timers are independently program-
mable and are reset by any transition on the TCLK and RCLK pins re-
spectively. The Watchdog timers will expire after approximately Wn
SYSCLK cycles (if not reset by transition on TCLK / RCLK pins) and
Provider Primitive 3 or 4 will be issued. The following table shows the
selections for Wn:
XWD1/RWD1
XWD0/RWD0
Wn
0
Disabled
01
2
18
10
2
19
11
2
20
11:10
0
Reserved, must be written as zero.
09:08
FWM
These bits define the FIFO watermarks. FIFO watermarks prevent
the MK50H27 from performing DMA transfers to/from the data buffers
until the FIFOs contain a minimum amount of data or space for data.
For receive
data, data will only be transferred to the data buffers
after the FIFO has at least N 16-bit words or an end of
signal
unit
has
been
reached.
Conversely,
for
transmit data, data will
only be transferred from the data buffers when the transmit FIFO
has room for at least N words of data. N is defined as follows:
FWM<1:0>
N
11
1 word
10*
9 words
01
17 words
00
25 words
* Suggested setting
07
BAE
Bus Address Enable: if BAE is set then the A23-A20 pins are driven
by the MK50H27 constantly providing the ability to use A23-A20 for
memory bus selection.
If clear, A23-A20 behave identically to A19-
A16.
06
BUSR
If this bit is set, pin 15 becomes input BUSREL. If this bit is clear
then pin 15 is either BM0 or BYTE depending on bit 00.
For more
information
see the description for pin 15 in this document. BUSR
is READ/WRITE and cleared on bus Reset.
05
BSWPC
This bit determines the byte ordering of all "non-data" DMA transfers.
1
5
1
0
1
4
0
9
1
2
1
0
8
0
3
0
7
0
2
0
6
0
5
0
4
0
1
0
1
3
B
S
W
P
C
B
U
R
S
T
1
:
0
B
S
W
P
D
A
C
O
N
B
C
O
N
F
W
M
B
A
E
B
U
S
R
X
W
D
1
X
W
D
0
R
W
D
1
R
W
D
0
MK50H27
21/56
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