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參數(shù)資料
| 型號： | MK2049-34SAITR |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 77.76 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 0.300 INCH, SOIC-20 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大小： | 148K |
| 代理商： | MK2049-34SAITR |
3.3 Volt Communications Clock VCXO PLL
MDS 2049-34A B
4
Revision 060105
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
MK2049-34A
Buffer Mode
Unlike the other two modes that accept only a single specified input frequency, Buffer Mode will accept a wider
range of input clocks. The input jitter is attenuated and the outputs on CLK and CLK/2 also provide the option of
getting x1, x2, x4, or 1/2 of the input frequency. For example, this mode can be used to remove the jitter from a 27
MHz clock, generating low-jitter 27 MHz and 13.5 MHz outputs.
Input and Output Synchronization
As shown in the tables on page 3, the MK2049-34A offers a Zero Delay feature in all selections. There is an internal
feedback path between ICLK and the output clocks, providing a fixed phase relationship between the input and
output, a requirement in many communication systems.
The rising edge of ICLK will be aligned with the rising edges of CLK and CLK/2 (8 kHz is used in this illustration, but
the same is true for the selections in the Loop Timing and Buffer Modes).
Measuring Zero Delay on the MK2049
The MK2049-34 produces low-jitter output clocks. In addition, this part has a very low bandwidth on the order of a
few Hertz. Since most 8 kHz input clocks will have high jitter, this can make measuring the input-to-output skew
(zero delay feature) very difficult. The MK2049 is designed to reject the input jitter; when the input and output clocks
are both displayed on an oscilloscope, they may appear not to be locked because the scope trigger point is
constantly changing with the input jitter. In fact, the input and output clocks probably are locked and the MK2049 will
have zero delay to the average position of the 8 kHz input clock. In order to see this clearly, a low jitter 8 kHz input
clock is necessary. Most lab frequency sources are NOT SUITABLE for this since they have high jitter at low
frequencies.
Frequency Locking to the Input
In all modes, the output clocks are frequency-locked to the input. The outputs will remain at the specified output
frequency as long as the combined variation of the input frequency and the crystal does not exceed 100 ppm. For
example, if the crystal can vary ±40 ppm (initial accuracy + temperature + aging), then the input frequency can vary
by up to 60 ppm and still have the output clock remain frequency-locked.
IC L K ( 8 k H z )
CL K ( M H z )
CL K /2 ( M H z )
Figu r e 1 . M K 2 0 4 9 - 3 4 Input a nd O u t put C loc k W a v e f o r m s
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MK2049-34SAILFTR | 77.76 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-34SAILF | 77.76 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-36SILFTR | 155.52 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-36SI | 155.52 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2059-01SILFTR | 25.92 MHz, OTHER CLOCK GENERATOR, PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2049-34SI | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-34SITR | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-35 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-35SI | 制造商:Integrated Device Technology Inc 功能描述:49.152 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-35SITR | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
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