- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄53727 > MK2049-34SAITR 77.76 MHz, OTHER CLOCK GENERATOR, PDSO20 PDF資料下載
參數(shù)資料
| 型號(hào)： | MK2049-34SAITR |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 77.76 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 0.300 INCH, SOIC-20 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 148K |
| 代理商： | MK2049-34SAITR |
3.3 Volt Communications Clock VCXO PLL
MDS 2049-34A B
2
Revision 060105
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
MK2049-34A
Pin Assignment
20-pin (300) mil SOIC
Pin Descriptions
16
1
15
2
14
FS1
FS0
3
13
X2
4
12
X1
RES
5
11
VDD
6
CAP2
7
FCAP
8
VDD
GND
CAP1
VDD
GND
CLK
ICLK
9
10
CLK/2
FS3
8k
FS2
20
19
18
17
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
FS1
Input
Frequency select 1. Determines CLK input/outputs per table on page 3.
2
X2
XO
Crystal connection. Connect to a MHz crystal as shown in table on page 3.
3
X1
XI
Crystal connection. Connect to a MHz crystal as shown in table on page 3.
4
VDD
Power
Power supply. Connect to +3.3 V.
5
FCAP
—
Filter capacitor. Connect a 1000 pF ceramic capacitor to ground.
6
VDD
Power
Power supply. Connect to +3.3 V.
7
GND
Power
Connect to ground
8
CLK
Output
Clock output determined by status of FS3:0 per tables on page 3.
9
CLK/2
Output
Clock output determined by status of FS3:0 per tables page 3. Always 1/2 of
CLK.
10
8k
Output
Recovered 8 kHz clock output.
11
FS2
Input
Frequency select 2. Determines CLK input/outputs per tables on page 3.
12
FS3
Input
Frequency select 3. Determines CLK input/outputs per tables on page 3.
13
ICLK
Input
Input clock connection. Connect to 8 kHz backplane or MHz clock.
14
GND
Power
Connect to ground.
15
VDD
Power
Power Supply. Connect to +3.3 V.
16
CAP1
Loop
Filter
Connect the loop filter ceramic capacitors and resistor between this pin and
CAP2.
17
GND
Power
Connect to ground.
18
CAP2
Loop
Connect the loop filter ceramic capacitors and resistor between this pin and
19
RES
—
Connect a 10-200k
resistor to ground. Contact ICS at telecom@icst.com for
recommended value for your application.
20
FS0
Input
Frequency select 0. Determines CLK input/outputs per table on page 3.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MK2049-34SAILFTR | 77.76 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-34SAILF | 77.76 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-36SILFTR | 155.52 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-36SI | 155.52 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2059-01SILFTR | 25.92 MHz, OTHER CLOCK GENERATOR, PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2049-34SI | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-34SITR | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-35 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-35SI | 制造商:Integrated Device Technology Inc 功能描述:49.152 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-35SITR | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。