參數(shù)資料
型號(hào): MFRC53101T
廠商: NXP Semiconductors N.V.
元件分類(lèi): 通信及網(wǎng)絡(luò)
英文描述: ISO-IEC 14443 reader IC
封裝: MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 51, 2004,;MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<
文件頁(yè)數(shù): 5/116頁(yè)
文件大小: 862K
代理商: MFRC53101T
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MFRC531_34
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.4 — 26 January 2010
056634
5 of 116
NXP Semiconductors
MFRC531
ISO/IEC 14443 reader IC
8.
Pinning information
8.1 Pin description
Fig 2.
MFRC531 pin configuration
MFRC531
OSCIN
OSCOUT
IRQ
RSTPD
MFIN
VMID
MFOUT
RX
TX1
AVSS
TVDD
AUX
TX2
AVDD
TVSS
DVDD
NCS
A2/SCK
NWR/R/NW/nWrite
A1
NRD/NDS/nDStrb
A0/nWait/MOSI
DVSS
ALE/AS/nAStrb/NSS
AD0/D0
D7/AD7
AD1/D1
D6/AD6
AD2/D2
D5/AD5
AD3/D3
D4/AD4
001aal219
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
18
17
20
19
22
21
24
23
26
25
32
31
30
29
28
27
Table 3.
Pin
1
Pin description
Symbol
OSCIN
Type
[1]
I
Description
oscillator/clock inputs:
crystal oscillator input to the oscillator’s inverting amplifier
externally generated clock input; f
osc
= 13.56 MHz
interrupt request generates an output signaling an interrupt event
ISO/IEC 14443 A MIFARE serial data interface input
ISO/IEC 14443 A MIFARE serial data interface output
transmitter 1 modulated carrier output; 13.56 MHz
transmitter power supply for the TX1 and TX2 output stages
transmitter 2 modulated carrier output; 13.56 MHz
transmitter ground for the TX1 and TX2 output stages
not chip select input: selects and activates the microprocessor interface
not write input: generates the strobe signal for writing data to the registers when
applied to pins D0 to D7
read not write input: switches between read or write cycles
not write input: selects the read or write cycle to be performed
not read input: generates the strobe signal for reading data from the registers
when applied to pins D0 to D7
not data strobe input: generates the strobe signal for the read and write cycles
not data strobe input: generates the strobe signal for the read and write cycles
digital ground
2
3
4
[2]
5
6
7
8
9
10
[3]
IRQ
MFIN
MFOUT
TX1
TVDD
TX2
TVSS
NCS
NWR
O
I
O
O
P
O
G
I
I
R/NW
nWrite
NRD
I
I
I
11
[3]
NDS
nDStrb
DVSS
I
I
G
12
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