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參數(shù)資料
| 型號： | MFRC52301HN1 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通信及網絡 |
| 英文描述： | Contactless reader IC |
| 封裝： | MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html& |
| 文件頁數(shù)： | 62/98頁 |
| 文件大小： | 1666K |
| 代理商： | MFRC52301HN1 |
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MFRC523
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
115237
62 of 98
NXP Semiconductors
MFRC523
Contactless reader IC
9.2.4.3
TestSel2Reg register
General test signal configuration and PRBS control.
Table 122. TestSel2Reg register (address 32h); reset value: 00h bit allocation
Bit
7
6
5
Symbol
TstBusFlip
PRBS9
PRBS15
Access
R/W
R/W
R/W
Table 123. TestSel2Reg register bit descriptions
Bit
Symbol
7
TstBusFlip
9.2.4.4
TestPinEnReg register
Enables the test bus pin output driver.
Table 124. TestPinEnReg register (address 33h); reset value: 80h bit allocation
Bit
7
6
5
Symbol
RS232LineEn
Access
R/W
Table 125. TestPinEnReg register bit descriptions
Bit
Symbol
Value
7
RS232LineEn
0
6 to 1 TestPinEn[5:0]
-
4
3
2
1
0
TestBusSel[4:0]
R/W
Value Description
1
test bus is mapped to the parallel port in the following order:
TstBusBit4,TstBusBit3, TstBusBit2, TstBusBit6, TstBusBit5,
TstBusBit0; see
Section 16.1 on page 80
-
starts and enables the PRBS9 sequence according to
ITU-TO150; the data transmission of the defined sequence is
started by the Transmit command
Remark:
all relevant registers to transmit data must be
configured before entering PRBS9 mode
-
starts and enables the PRBS15 sequence according to
ITU-TO150; the data transmission of the defined sequence is
started by the Transmit command
Remark:
all relevant registers to transmit data must be
configured before entering PRBS15 mode
6
PRBS9
5
PRBS15
4 to 0 TestBusSel[4:0]
-
selects the test bus; see
Section 16.1 “Test signals” on page 80
4
3
2
1
0
TestPinEn[5:0]
R/W
reserved
-
Description
serial UART lines MX and DTRQ are disabled
enables the output driver on one of the data pins D1 to D7 which
outputs a test signal
Example:
setting bit 1 to logic 1 enables pin D1 output
setting bit 5 to logic 1 enables pin D5 output
Remark:
If the SPI is used, only pins D1 to D4 can be used. If the
serial UART interface is used and the RS232LineEn bit is set to
logic 1 only pins D1 to D4 can be used.
reserved for future use
0
reserved
-
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| MFRC52301HN1,151 | 功能描述:RFID應答器 IC TRANSMISSION MOD 32-HVQFN RoHS:否 制造商:Murata 存儲容量:512 bit 工作溫度范圍:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
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