參數(shù)資料
型號: MFRC52301HN1
廠商: NXP Semiconductors N.V.
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Contactless reader IC
封裝: MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html&
文件頁數(shù): 61/98頁
文件大小: 1666K
代理商: MFRC52301HN1
MFRC523
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
115237
61 of 98
NXP Semiconductors
MFRC523
Contactless reader IC
Table 115. TCounterValReg register higher bit descriptions
Bit
Symbol
7 to 0
TCounterVal_Hi[7:0] timer value higher 8 bits
Table 116. TCounterValReg (lower bits) register (address 2Fh); reset value: xxh bit
allocation
Bit
7
6
5
Symbol
TCounterVal_Lo[7:0]
Access
Table 117. TCounterValReg register lower bit descriptions
Bit
Symbol
7 to 0
TCounterVal_Lo[7:0]
9.2.4
Page 3: Test
9.2.4.1
Reserved register 30h
Functionality is reserved for future use.
Table 118. Reserved register (address 30h); reset value: 00h bit allocation
Bit
7
6
5
Symbol
Access
Table 119. Reserved register bit descriptions
Bit
Symbol
7 to 0
reserved
9.2.4.2
TestSel1Reg register
General test signal configuration.
Table 120. TestSel1Reg register (address 31h); reset value: 00h bit allocation
Bit
7
6
5
Symbol
reserved
Access
-
Table 121. TestSel1Reg register bit descriptions
Bit
Symbol
7 to 3
reserved
2 to 0
TstBusBitSel[2:0]
Description
4
3
2
1
0
R
Description
timer value lower 8 bits
4
3
2
1
0
reserved
-
Description
reserved for future use
4
3
2
1
0
TstBusBitSel[2:0]
R/W
Description
reserved for future use
selects a test bus signal which is output at pin MFOUT. If
AnalogSelAux2[3:0] = FFh in AnalogTestReg register, test bus
signal is also output at pins AUX1 or AUX2
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