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| 型號： | MFRC52301HN1 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Contactless reader IC |
| 封裝： | MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html& |
| 文件頁數(shù)： | 31/98頁 |
| 文件大?。?/td> | 1666K |
| 代理商： | MFRC52301HN1 |
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MFRC523
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
115237
31 of 98
NXP Semiconductors
MFRC523
Contactless reader IC
for further access to the registers. To ensure this, perform a read access to address 0 until
the MFRC523 answers to the last read command with the register content of address 0.
This indicates that the MFRC523 is ready.
8.8.3
Transmitter Power-down mode
The Transmitter Power-down mode switches off the internal antenna drivers and the RF
field. Transmitter Power-down mode is entered by setting either the TxControlReg
register’s Tx1RFEn bit or Tx2RFEn bit to logic 0.
8.9 Oscillator circuit
The clock applied to the MFRC523 provides a time basis for the synchronous system’s
encoder and decoder. The stability of the clock frequency is an important factor for correct
operation. To obtain optimum performance, clock jitter must be reduced as much as
possible. This is best achieved using the internal oscillator buffer with the recommended
circuitry.
If an external clock source is used, the clock signal must be applied to pin OSCIN. In this
case, be very careful in optimizing clock duty cycle and clock jitter. Ensure the clock
quality has been verified.
8.10 Reset and oscillator start-up time
8.10.1
Reset timing requirements
The reset signal is filtered by a hysteresis circuit and a spike filter before it enters the
digital circuit. The spike filter rejects signals shorter than 10 ns. In order to perform a reset,
the signal must be LOW for at least 100 ns.
8.10.2
Oscillator start-up time
If the MFRC523 has been set to a Power-down mode or is powered by a V
DDX
supply, the
start-up time for the MFRC523 depends on the oscillator used and is shown in
Figure 23
.
The time (t
startup
) is the start-up time of the crystal oscillator circuit. The crystal oscillator
start-up time is defined by the crystal.
The time (t
d
) is the internal delay time of the MFRC523 when the clock signal is stable
before the MFRC523 can be addressed.
Fig 22. Quartz crystal connection
001aal162
MFRC523
27.12 MHz
OSCOUT
OSCIN
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| MFRC52301HN1,151 | 功能描述:RFID應(yīng)答器 IC TRANSMISSION MOD 32-HVQFN RoHS:否 制造商:Murata 存儲容量:512 bit 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| MFRC52301HN1,157 | 功能描述:RFID應(yīng)答器 IC TRANSMISSION MOD 32-HVQFN RoHS:否 制造商:Murata 存儲容量:512 bit 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| MFRC52301HN1/TRAYB | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Contactless reader IC |
| MFRC52301HN1/TRAYBM | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Contactless reader IC |
| MFRC52302HN1,151 | 功能描述:RFID應(yīng)答器 CONTACTLESS READER IC RoHS:否 制造商:Murata 存儲容量:512 bit 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
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