參數(shù)資料
型號: MCIMX31DVMN5D
廠商: Freescale Semiconductor
文件頁數(shù): 72/118頁
文件大?。?/td> 0K
描述: IC MPU I.MX31 CONSUMR 473MAPBGA
標準包裝: 84
系列: i.MX31
核心處理器: ARM11
芯體尺寸: 32-位
速度: 532MHz
連通性: 1 線,ATA,EBI/EMI,F(xiàn)IR,I²C,MMC/SD,PCMCIA,SIM,SPI,SSI,UART/USART,USB,USB OTG
外圍設備: DMA,LCD,POR,PWM,WDT
程序存儲器類型: ROMless
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.22 V ~ 3.3 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 473-LFBGA
包裝: 托盤
Electrical Characteristics
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
57
The timing described in Figure 43 is that of a Motorola sensor. Some other sensors may have a slightly
different timing. The CSI can be programmed to support rising/falling-edge triggered SENSB_VSYNC;
active-high/low SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK.
4.3.14.3
Electrical Characteristics
Figure 44 depicts the sensor interface timing, and Table 44 lists the timing parameters.
Figure 44. Sensor Interface Timing Diagram
4.3.15
IPUDisplay Interfaces
4.3.15.1
Supported Display Components
Table 45 lists the known supported display components at the time of publication.
Table 44. Sensor Interface Timing Parameters1
1 The timing specifications for Figure 44 are referenced to the rising edge of SENS_PIX_CLK when the
SENS_PIX_CLK_POL bit in the CSI_SENS_CONF register is cleared. When the SENS_PIX_CLK_POL is set,
the clock is inverted and all timing specifications will remain the same but are referenced to the falling edge of
the clock.
ID
Parameter
Symbol
Min.
Max.
Units
IP1
Sensor input clock frequency
Fmck
0.01
133
MHz
IP2
Data and control setup time
Tsu
5
ns
IP3
Data and control holdup time
Thd
3
ns
IP4
Sensor output (pixel) clock frequency
Fpck
0.01
133
MHz
SENSB_MCLK
IP3
SENSB_DATA,
SENSB_VSYNC,
IP2
1/IP1
1/IP4
SENSB_PIX_CLK
(Sensor Input)
(Sensor Output)
SENSB_HSYNC
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