參數(shù)資料
型號: MCIMX31DVMN5D
廠商: Freescale Semiconductor
文件頁數(shù): 55/118頁
文件大小: 0K
描述: IC MPU I.MX31 CONSUMR 473MAPBGA
標準包裝: 84
系列: i.MX31
核心處理器: ARM11
芯體尺寸: 32-位
速度: 532MHz
連通性: 1 線,ATA,EBI/EMI,F(xiàn)IR,I²C,MMC/SD,PCMCIA,SIM,SPI,SSI,UART/USART,USB,USB OTG
外圍設備: DMA,LCD,POR,PWM,WDT
程序存儲器類型: ROMless
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.22 V ~ 3.3 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 473-LFBGA
包裝: 托盤
Electrical Characteristics
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
41
NOTE
High is defined as 80% of signal value and low is defined as 20% of signal
value.
Test conditions: load capacitance, 25 pF. Recommended drive strength for all
controls, address, and BCLK is Max drive.
basic WEIM accesses to external memory devices with the timing parameters mentioned in
Table 32 for specific control parameter settings.
WE8
Clock rise/fall to OE Invalid
–3
3
ns
WE9
Clock rise/fall to EB[x] Valid
–3
3
ns
WE10
Clock rise/fall to EB[x] Invalid
–3
3
ns
WE11
Clock rise/fall to LBA Valid
–3
3
ns
WE12
Clock rise/fall to LBA Invalid
–3
3
ns
WE13
Clock rise/fall to Output Data Valid
–2.5
4
ns
WE14
Clock rise to Output Data Invalid
–2.5
4
ns
WE15
Input Data Valid to Clock rise, FCE=0
FCE=1
8
2.5
ns
WE16
Clock rise to Input Data Invalid, FCE=0
FCE=1
–2
ns
WE17
ECB setup time, FCE=0
FCE=1
6.5
3.5
ns
WE18
ECB hold time, FCE=0
FCE=1
–2
2
ns
WE19
DTACK setup time1
0—
ns
WE20
DTACK hold time1
4.5
ns
WE21
BCLK High Level Width2, 3
—T/2 – 3
ns
WE22
BCLK Low Level Width2, 3
—T/2 – 3
ns
WE23
BCLK Cycle time2
15
ns
1 Applies to rising edge timing
2 BCLK parameters are being measured from the 50% VDD.
3 The actual cycle time is derived from the AHB bus clock frequency.
Table 32. WEIM Bus Timing Parameters (continued)
ID
Parameter
Min
Max
Unit
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