參數(shù)資料
型號: MCIMX31DVMN5D
廠商: Freescale Semiconductor
文件頁數(shù): 71/118頁
文件大小: 0K
描述: IC MPU I.MX31 CONSUMR 473MAPBGA
標(biāo)準(zhǔn)包裝: 84
系列: i.MX31
核心處理器: ARM11
芯體尺寸: 32-位
速度: 532MHz
連通性: 1 線,ATA,EBI/EMI,F(xiàn)IR,I²C,MMC/SD,PCMCIA,SIM,SPI,SSI,UART/USART,USB,USB OTG
外圍設(shè)備: DMA,LCD,POR,PWM,WDT
程序存儲(chǔ)器類型: ROMless
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.22 V ~ 3.3 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 473-LFBGA
包裝: 托盤
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
56
Freescale Semiconductor
Electrical Characteristics
4.3.14.2.2
Gated Clock Mode
The SENSB_VSYNC, SENSB_HSYNC, and SENSB_PIX_CLK signals are used in this mode. See
Figure 42. Gated Clock Mode Timing Diagram
A frame starts with a rising edge on SENSB_VSYNC (all the timings correspond to straight polarity of the
corresponding signals). Then SENSB_HSYNC goes to high and hold for the entire line. Pixel clock is
valid as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks.
SENSB_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI stops
receiving data from the stream. For next line the SENSB_HSYNC timing repeats. For next frame the
SENSB_VSYNC timing repeats.
4.3.14.2.3
Non-Gated Clock Mode
The timing is the same as the gated-clock mode (described in Section 4.3.14.2.2, “Gated Clock Mode”),
except for the SENSB_HSYNC signal, which is not used. See Figure 43. All incoming pixel clocks are
valid and will cause data to be latched into the input FIFO. The SENSB_PIX_CLK signal is inactive (states
low) until valid data is going to be transmitted over the bus.
Figure 43. Non-Gated Clock Mode Timing Diagram
SENSB_VSYNC
SENSB_HSYNC
SENSB_PIX_CLK
SENSB_DATA[9:0]
invalid
1st byte
n+1th frame
invalid
1st byte
nth frame
Active Line
Start of Frame
SENSB_VSYNC
SENSB_PIX_CLK
SENSB_DATA[7:0]
invalid
1st byte
n+1th frame
invalid
1st byte
nth frame
Start of Frame
相關(guān)PDF資料
PDF描述
MCIMX31VMN5CR2 IC MPU MAP I.MX31L 473-MAPBGA
MCIMX353CJQ5CR2 MULTIMEDIA PROCESSOR 400-MAPBGA
MCIMX356AJM5BR2 IC MPU IMX35 ARM11 400MAPBGA
MCIMX515DJZK8C IC MPU I.MX51 527MAPBGA
MCIMX537CVV8B MULTIMEDIA PROC 529-TEPBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MCIMX31DVMN5DR2 功能描述:處理器 - 專門應(yīng)用 2.0.1 CONSUMER FULL RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MCIMX31L 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Multimedia Applications Processors
MCIMX31LC 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Multimedia Applications Processors for Industrial and Automotive Products
MCIMX31LCJKN5D 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Multimedia Applications Processors
MCIMX31LCJMN4D 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Multimedia Applications Processors for Industrial and Automotive Products