參數(shù)資料
型號(hào): MCF5484CZP200
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388
封裝: 27 X 27 MM, 1 MM PITCH, PLASTIC, MS-034AAL-1, BGA-388
文件頁數(shù): 88/96頁
文件大?。?/td> 2006K
代理商: MCF5484CZP200
MOTOROLA
MCF548x Integrated Microprocessor Hardware Specifications
89
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Document Revision History
Figure 40 shows timing for the values in Table 38 and Table 39.
Figure 40. I2C Input/Output Timings
A.14 JTAG and Boundary Scan Timing
Table 39. I2C Output Timing Specifications between SCL and SDA
Num
Characteristic
Min
Max
Units
I1 1
1
Note: Output numbers depend on the value programmed into the IFDR; an IFDR programmed
with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in
Table 39. The I2C interface is designed to scale the actual data transition time to move it to the
middle of the SCL low period. The actual position is affected by the prescale and division values
programmed into the IFDR; however, the numbers given in Table 39 are minimum values.
Start condition hold time
6
Bus clocks
I2 1
Clock low period
10
Bus clocks
I3 2
2
Because SCL and SDA are open-collector-type outputs, which the processor can only actively
drive low, the time SCL or SDA take to reach a high level depends on external signal
capacitance and pull-up resistor values.
SCL/SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
S
I4 1
Data hold time
7
Bus clocks
I5 3
3
Specified at a nominal 50-pF load.
SCL/SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
3
ns
I6 1
Clock high time
10
Bus clocks
I7 1
Data setup time
2
Bus clocks
I8 1
Start condition setup time (for repeated start
condition only)
20
Bus clocks
I9 1
Stop condition setup time
10
Bus clocks
Table 40. JTAG and Boundary Scan Timing
Num
Symbol
Min
Max
Unit
J1
TCLK Frequency of Operation
fJCYC
DC
10
MHz
J2
TCLK Cycle Period
tJCYC
2—
tCK
J3
TCLK Clock Pulse Width
tJCW
15.15
ns
J4
TCLK Rise and Fall Times
tJCRF
0.0
3.0
ns
SCL
I2
I6
I1
I4
I5
I7
I8
I3
I9
SDA
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