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參數(shù)資料
| 型號： | MCF5484CZP200 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388 |
| 封裝： | 27 X 27 MM, 1 MM PITCH, PLASTIC, MS-034AAL-1, BGA-388 |
| 文件頁數(shù)： | 22/96頁 |
| 文件大?。?/td> | 2006K |
| 代理商： | MCF5484CZP200 |
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MOTOROLA
MCF548x Integrated Microprocessor Hardware Specifications
29
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Signal Description
chip select can be programmed for a base address location, masking addresses, port size, burst-capability
indication, wait-state generation, and internal/external termination.
Reset clears all chip select programming; FBCS0 is the only chip select initialized out of reset. FBCS0 is
also unique because it can function at reset as a global chip select that allows boot ROM to be selected at
any defined address space. Port size and termination (internal vs. external) for boot FBCS0 are configured
by the levels on AD[2:0] on the rising edge of RSTI, as described in Section 1.5.1.6, “Reset Configuration
1.5.1.1.3
Transfer Start (TS)
The assertion of TS indicates that the MCF548x has begun a bus transaction and that the address and
attributes are valid. TS is asserted for one bus clock cycle. TS can be used externally as address latch enable
to capture the address phase of the bus transfer.
1.5.1.1.4
Read/Write (R/W)
The MCF548x drives the R/W signal to indicate the direction of the current bus operation. It is driven high
during read bus cycles and driven low during write bus cycles.
1.5.1.1.5
Transfer Burst (TBST)
Transfer burst indicates that a burst transfer is in progress. A burst transfer can be 2 to 16 beats depending
on the size of the transfer and the port size.
1.5.1.1.6
Transfer Size (TSIZ[1:0])
For memory accesses, these signals along with TBST, indicate the data transfer size of the current bus
operation. The FlexBus interface supports byte, word, and longword operand transfers and allows accesses
to 8-, 16-, and 32-bit data ports.
For misaligned transfers, TSIZ[1:0] indicate the size of each transfer. For example, if a longword access
through a 32-bit port device occurs at a misaligned offset of 0x1, a byte is transferred first (TSIZ[1:0] = 01),
a word is next transferred at offset 0x2 (TSIZ[1:0] = 10), then the final byte is transferred at offset 0x4
(TSIZ[1:0] = 01).
For aligned transfers larger than the port size, TSIZ[1:0] behaves as follows:
If bursting is used, TSIZ[1:0] is driven to the size of transfer.
If bursting is inhibited, TSIZ[1:0] first shows the size of the entire transfer and then shows the port
size
.
Table 5. Data Transfer Size
TSIZ[1:0]
Transfer Size
00
4 bytes (longword)
01
1 byte
10
2 bytes (word)
11
16 bytes (line)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MCF5485CVR200 | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388 |
| MCF5483CVR166 | 32-BIT, 166.66 MHz, RISC PROCESSOR, PBGA388 |
| MCF5481CZP166 | 32-BIT, 166.66 MHz, RISC PROCESSOR, PBGA388 |
| MCF5484CVR200 | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388 |
| MCF5481CVR166 | 32-BIT, 166.66 MHz, RISC PROCESSOR, PBGA388 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCF5485 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCF548x ColdFire㈢ Microprocessor |
| MCF5485CVR200 | 功能描述:微處理器 - MPU MCF548X V4ECORE MMU FPU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MCF5485CZP200 | 功能描述:微處理器 - MPU MCF548X V4ECORE MMU FPU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MCF548X | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCF548x ColdFire㈢ Microprocessor |
| MCF548X_07 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCF548x ColdFire㈢ Microprocessor |
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