參數(shù)資料
型號(hào)： MCF5484CZP200
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388
封裝： 27 X 27 MM, 1 MM PITCH, PLASTIC, MS-034AAL-1, BGA-388
文件頁(yè)數(shù)： 81/96頁(yè)
文件大?。?/td> 2006K
代理商： MCF5484CZP200
82
MCF548x Integrated Microprocessor Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Document Revision History
Figure 32. DDR Clock Timing Diagram
Table 31. DDR Timing Specifications
Symbol
Characteristic
Min
Max
Unit
Notes
Frequency of Operation
83
133
MHz
1
The frequency of operation is either 2x or 4x the CLKIN frequency of operation. The MCF548X supports a single
external reference clock (CLKIN). This signal defines the frequency of operation for both FlexBus and PCI, but
SDRAM clock operates at the same frequency as the internal bus clock. Please see the PLL chapter for more
information on setting the SDRAM clock rate.
DD1
Clock Period (tCK)7.52
12
ns
2
SDCLK is one memory clock in (ns).
DD2
Pulse Width High (tCKH)
0.45
0.55
SDCLK
3
Pulse width high plus pulse width low cannot exceed max clock period.
DD3
Pulse Width Low (tCKL)
0.45
0.55
SDCLK
4
Pulse width high plus pulse width low cannot exceed max clock period.
DD4
Address, SDCKE, CAS, RAS, WE, SDBA, SDCS - Output
Valid (tCMV)
—
0.5*SDCLK+
1.0 ns
ns
DD5
Address, SDCKE, CAS, RAS, WE, SDBA, SDCS - Output
Hold (tCMH)
2.0
—
ns
DD6
Write Command to first DQS Latching Transition (tDQSS)
—
1.25
SDCLK
DD7
Data and Data Mask Output Setup (DQ-->DQS) Relative
to DQS (DDR Write Mode) (tQS)
1.5
—
ns
5
6
5
This specification relates to the required input setup time of today’s DDR memories. SDDATA[31:24] is relative to
SDDQS3, SDDATA[23:16] is relative to SDDQS2, SDDATA[15:8] is relative to SDDQS1, and SDDATA[7:0] is
relative SDDQS0.
DD8
Data and Data Mask Output Hold (DQS-->DQ) Relative to
DQS (DDR Write Mode) (tQH)
1.0
—
ns
7
DD9
Input Data Skew Relative to DQS (Input Setup) (tIS)1
ns
8
DD10
Input Data Hold Relative to DQS (tIH)
0.25*SDCLK
+0.5ns
—ns
9
DD11
DQS falling edge to SDCLK rising (output setup time)
(tDSS)
0.5
—
ns
DD12
DQS falling edge from SDCLK rising (output hold time)
(tDSH)
0.5
—
ns
DD13
DQS input read preamble width (tRPRE)
0.9
1.1
SDCLK
DD14
DQS input read postamble width (tRPST)
0.4
0.6
SDCLK
DD15
DQS output write preamble width (tWPRE)
0.25
—
SDCLK
DD16
DQS output write postamble width (tWPST)
0.4
0.6
SDCLK
VIX
VMP
VIX
VID
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