MC9328MX21 Technical Data, Rev. 3.4
92
Freescale Semiconductor
Specifications
3.21
I2C Module
The I2C communication protocol consists of seven elements: START, Data Source/Recipient, Data
Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP.
Figure 80. Definition of Bus Timing for I2C
3.22
CMOS Sensor Interface
The CSI module consists of a control register to configure the interface timing, a control register for
statistic data generation, a status register, interface logic, a 32
× 32 image data receive FIFO, and a 16 × 32
statistic data FIFO.
3.22.1
Gated Clock Mode
Figure 81 shows the timing diagram when the CMOS sensor output data is configured for negative edge
and the CSI is programmed to received data on the positive edge.
Figure 82 shows the timing diagram
when the CMOS sensor output data is configured for positive edge and the CSI is programmed to received
data in negative edge. The parameters for the timing diagrams are listed in
Table 45. The formula for
Table 44. I2C Bus Timing Parameters
Ref
No.
Parameter
1.8 V
± 0.1 V
3.0 V
± 0.3 V
Unit
Minimum
Maximum
Minimum
Maximum
SCL Clock Frequency
0
100
0
100
kHz
1
Hold time (repeated) START condition
114.8
–
111.1
–
ns
2
Data hold time
0
69.7
0
72.3
ns
3
Data setup time
3.1
–
1.76
–
ns
4
HIGH period of the SCL clock
69.7
–
68.3
–
ns
5
LOW period of the SCL clock
336.4
–
335.1
–
ns
6
Setup time for STOP condition
110.5
–
111.1
–
ns
SDA
SCL
1
2
3
4
6
5