參數(shù)資料
型號： MC9328MX21CVKR2
廠商： Freescale Semiconductor
文件頁數(shù)： 46/100頁
文件大?。?/td> 0K
描述： IC MCU I.MX21 266MHZ 289-MAPBGA
標準包裝： 1,000
系列： i.MX21
核心處理器： ARM9
芯體尺寸： 32-位
速度： 266MHz
連通性： 1 線，EBI/EMI，I²C，IrDA，MMC，智能卡，SPI，SSI，UART/USART，USB OTG
外圍設備： DMA，I²S，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 192
程序存儲器類型： ROMless
電壓 - 電源 (Vcc/Vdd)： 1.45 V ~ 3.3 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 289-LFBGA
包裝： 帶卷 (TR)
Signal Descriptions
MC9328MX21 Technical Data, Rev. 3.4
Freescale Semiconductor
5
Memory Interface
— External Interface Module (EIM)
— SDRAM Controller (SDRAMC)
— NAND Flash Controller (NFC)
— PCMCIA/CF Interface
Standard System Resources
— Clock Generation Module (CGM) and Power Control Module
— Three General-Purpose 32-Bit Counters/Timers
— Watchdog Timer
— Real-Time Clock/Sampling Timer (RTC)
— Pulse-Width Modulator (PWM) Module
— Direct Memory Access Controller (DMAC)
— General-Purpose I/O (GPIO) Ports
— Debug Capability
2
Signal Descriptions
Table 2 identifies and describes the i.MX21 signals. Pin assignment is provided in Section 4, “Pin
Assignment and Package Information” and in the “Signal Multiplexing Scheme” table within the reference
manual.
The connections of the pins in Table 2 depends solely upon the user application, however there are a few
factory test signals that are not used in a normal application. Following is a list of these signals and how
they are to be terminated for proper operation of the i.MX21 processor:
CLKMODE[1:0]: To ensure proper operation, leave these signals as no connects.
OSC26M_TEST: To ensure proper operation, leave this signal as no connect.
EXT_48M: To ensure proper operation, connect this signal to ground.
EXT_266M: To ensure proper operation, connect this signal to ground.
TEST_WB[2:0]: These signals are also multiplexed with GPIO PORT E as well as alternate
keypad signals. If not utilizing these signals for GPIO functionality or for their other multiplexed
function, then configure as GPIO input with pull up enabled, and leave as a no connect.
TEST_WB[4:3]: To ensure proper operation, leave these signals as no connects.
Table 2. i.MX21 Signal Descriptions
Signal Name
Function/Notes
External Bus/Chip Select (EIM)
A [25:0]
Address bus signals
D [31:0]
Data bus signals
EB0
MSB Byte Strobe—Active low external enable byte signal that controls D [31:24], shared with SDRAM
DQM0.
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