- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1950 > MC9328MX21CVKR2 (Freescale Semiconductor)IC MCU I.MX21 266MHZ 289-MAPBGA PDF資料下載
參數(shù)資料
| 型號： | MC9328MX21CVKR2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 68/100頁 |
| 文件大小： | 0K |
| 描述： | IC MCU I.MX21 266MHZ 289-MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | i.MX21 |
| 核心處理器： | ARM9 |
| 芯體尺寸： | 32-位 |
| 速度： | 266MHz |
| 連通性： | 1 線，EBI/EMI，I²C，IrDA，MMC，智能卡，SPI，SSI，UART/USART，USB OTG |
| 外圍設(shè)備： | DMA，I²S，LCD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 192 |
| 程序存儲器類型： | ROMless |
| 電壓 - 電源 (Vcc/Vdd)： | 1.45 V ~ 3.3 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 289-LFBGA |
| 包裝： | 帶卷 (TR) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁當(dāng)前第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁
Signal Descriptions
MC9328MX21 Technical Data, Rev. 3.4
Freescale Semiconductor
7
Clocks and Resets
EXTAL26M
Crystal input (26MHz), or a 16 MHz to 32 MHz oscillator (or square-wave) input when the internal
oscillator circuit is shut down. When using an external signal source, feed this input with a square wave
signal switching from GND to VDDA.
XTAL26M
Oscillator output to external crystal. When using an external signal source, float this output.
EXTAL32K
32 kHz or 32.768 kHz crystal input. When using an external signal source, feed this input with a square
wave signal switching from GND to QVDD5.
XTAL32K
Oscillator output to external crystal. When using an external signal source, float this output.
CLKO
Clock Out signal selected from internal clock signals. Please refer to clock controller for internal clock
selection.
EXT_48M
This is a special factory test signal. To ensure proper operation, connect this signal to ground.
EXT_266M
This is a special factory test signal. To ensure proper operation, connect this signal to ground.
RESET_IN
Master Reset—External active low Schmitt trigger input signal. When this signal goes active, all modules
(except the reset module, SDRAMC module, and the clock control module) are reset.
RESET_OUT
Reset Out—Internal active low output signal from the Watchdog Timer module and is asserted from the
following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out.
POR
Power On Reset—Active low Schmitt trigger input signal. The POR signal is normally generated by an
external RC circuit designed to detect a power-up event.
CLKMODE[1:0]
These are special factory test signals. To ensure proper operation, leave these signals as no connects.
OSC26M_TEST
This is a special factory test signal. To ensure proper operation, leave this signal as a no connect.
TEST_WB[2:0]
These are special factory test signals. However, these signals are also multiplexed with GPIO PORT E
as well as alternate keypad signals. If not using these signals for GPIO functions or for other multiplexed
functions, then configure as GPIO input with pull-up enabled, and leave as a no connect.
TEST_WB[4:3]
These are special factory test signals. To ensure proper operation, leave these signals as no connects.
WKGD
Battery indicator input used to qualify the walk-up process. Also multiplexed with TIN.
JTAG
For termination recommendations, see the Table “JTAG pinouts” in the Multi-ICE User Guide from ARM Limited.
TRST
Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.
TDO
Serial Output for test instructions and data. Changes on the falling edge of TCK.
TDI
Serial Input for test instructions and data. Sampled on the rising edge of TCK.
TCK
Test Clock to synchronize test logic and control register access through the JTAG port.
TMS
Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge of
TCK.
JTAG_CTRL
JTAG Controller select signal—JTAG_CTRL is sampled during the rising edge of TRST. Must be pulled
to logic high for proper JTAG interface to debugger. Pulling JTAG_CRTL low is for internal test purposes
only.
RTCK
JTAG Return Clock used to enhance stability of JTAG debug interface devices. This signal is multiplexed
with 1-Wire, therefore using 1-Wire renders RTCK unusable and vice versa.
CMOS Sensor Interface
CSI_D [7:0]
Sensor port data
CSI_MCLK
Sensor port master clock
Table 2. i.MX21 Signal Descriptions (Continued)
Signal Name
Function/Notes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC9328MX21SCVKR2 | IC MCU I.MX21 266MHZ 289-MAPBGA |
| MC9328MXLVM20 | IC MCU I.MX 200MHZ 256-MAPBGA |
| MC9328MXSCVP10 | IC MCU I.MXS 100MHZ 225-MAPBGA |
| MC9RS08KA1CDBR | IC CPU RS08 1K FLASH 62RAM 6-DFN |
| MC9RS08KB2CSC | MCU 8-BIT 2K FLASH 8-SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC9328MX21CVM | 功能描述:處理器 - 專門應(yīng)用 DB I.MX21 17X17 PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MC9328MX21CVM | 制造商:Freescale Semiconductor 功能描述:Microprocessor |
| MC9328MX21CVMR2 | 功能描述:處理器 - 專門應(yīng)用 DB I.MX21 17X17 PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MC9328MX21DVG | 制造商:Rochester Electronics LLC 功能描述:DB I.MX21 - Bulk 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述: |
| MC9328MX21DVGR2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。