參數(shù)資料
型號(hào)： MC9328MX21CVKR2
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 4/100頁(yè)
文件大?。?/td> 0K
描述： IC MCU I.MX21 266MHZ 289-MAPBGA
標(biāo)準(zhǔn)包裝： 1,000
系列： i.MX21
核心處理器： ARM9
芯體尺寸： 32-位
速度： 266MHz
連通性： 1 線，EBI/EMI，I²C，IrDA，MMC，智能卡，SPI，SSI，UART/USART，USB OTG
外圍設(shè)備： DMA，I²S，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 192
程序存儲(chǔ)器類型： ROMless
電壓 - 電源 (Vcc/Vdd)： 1.45 V ~ 3.3 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 289-LFBGA
包裝： 帶卷 (TR)
Signal Descriptions
MC9328MX21 Technical Data, Rev. 3.4
Freescale Semiconductor
11
General Purpose Timers
TIN
Timer Input Capture or Timer Input Clock—The signal on this input is applied to all 3 timers
simultaneously. This signal is muxed with the Walk-up Guard Mode WKGD signal in the PLL, Clock, and
Reset Controller module.
TOUT1
(or simply TOUT)
Timer Output signal from General Purpose Timer1 (GPT1). This signal is multiplexed with SYS_CLK1
and SYS_CLK2 signal of SSI1 and SSI2. The pin name of this signal is simply TOUT.
TOUT2
Timer Output signal from General Purpose Timer1 (GPT2). This signal is multiplexed with PWMO.
TOUT3
Timer Output signal from General Purpose Timer1 (GPT3). This signal is multiplexed with PWMO.
USB On-The-Go
USB_BYP
USB Bypass input active low signal. This signal can only be used for USB function, not for GPIO.
USB_PWR
USB Power output signal
USB_OC
USB Over current input signal. This signal can only be used for USB function, not for GPIO.
USBG_RXDP
USB OTG Receive Data Plus input signal. This signal is muxed with SLCDC1_DAT15.
USBG_RXDM
USB OTG Receive Data Minus input signal. This signal is muxed with SLCDC1_DAT14.
USBG_TXDP
USB OTG Transmit Data Plus output signal. This signal is muxed with SLCDC1_DAT13.
USBG_TXDM
USB OTG Transmit Data Minus output signal. This signal is muxed with SLCDC1_DAT12.
USBG_RXDAT
USB OTG Transceiver differential data receive signal. Multiplexed with CSPI1_SS2.
USBG_OE
USB OTG Output Enable signal. This signal is muxed with SLCDC1_DAT11.
USBG_ON
USB OTG Transceiver ON output signal. This signal is muxed with SLCDC1_DAT9.
USBG_FS
USB OTG Full Speed output signal. This signal is multiplexed with external transceiver USBG_TXR_INT
signal of USB OTG. This signal is muxed with SLCDC1_DAT10.
USBH1_RXDP
USB Host1 Receive Data Plus input signal. This signal is multiplexed with UART4_RXD and
SLCDC1_DAT6. It also provides an alternative multiplex for UART4_RTS, where this signal is selectable
by programming the Function Multiplexing Control Register in the System Control chapter.
USBH1_RXDM
USB Host1 Receive Data Minus input signal. This signal is muxed with SLCDC1_DAT5. It also provides
an alternative multiplex for UART4_CTS.
USBH1_TXDP
USB Host1 Transmit Data Plus output signal. This signal is multiplexed with UART4_CTS and
SLCDC1_DAT4. It also provides an alternative multiplex for UART4_RXD, where this signal is selectable
by programming the Function Multiplexing Control Register in the System Control chapter.
USBH1_TXDM
USB Host1 Transmit Data Minus output signal. Multiplexed with UART4_TXD and SLCDC1_DAT3.
USBH1_RXDAT
USB Host1 Transceiver differential data receive signal. Multiplexed with USBH1_FS.
USBH1_OE
USB Host1 Output Enable signal. This signal is muxed with SLCDC1_DAT2.
USBH1_FS
USB Host1 Full Speed output signal. Multiplexed with UART4_RTS and SLCDC1_DAT1 and
USBH1_RXDAT.
USBH_ON
USB Host transceiver ON output signal. This signal is muxed with SLCDC1_DAT0.
USBH2_RXDP
USB Host2 Receive Data Plus input signal. This signal is multiplexed with CSPI2_SS[1] of CSPI2.
USBH2_RXDM
USB Host2 Receive Data Minus input signal. This signal is multiplexed with CSPI2_SS[2] of CSPI2.
USBH2_TXDP
USB Host2 Transmit Data Plus output signal. This signal is multiplexed with CSPI2_MOSI of CSPI2.
USBH2_TXDM
USB Host2 Transmit Data Minus output signal. This signal is multiplexed with CSPI2_MISO of CSPI2.
USBH2_OE
USB Host2 Output Enable signal. This signal is multiplexed with CSPI2_SCLK of CSPI2.
Table 2. i.MX21 Signal Descriptions (Continued)
Signal Name
Function/Notes
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