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參數(shù)資料
| 型號： | MC68HC16Z1VEH16 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 44/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 16BIT 1K FLASH 132-PQFP |
| 標準包裝： | 36 |
| 系列： | HC16 |
| 核心處理器： | CPU16 |
| 芯體尺寸： | 16-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，SCI，SPI |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 16 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 132-BQFP 緩沖式 |
| 包裝： | 托盤 |
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6. If the value of the series resistor is correct, check for the presence of metastable states during
power-up. If there is extremely high frequency oscillation on the CLKOUT pin during the first few
hundred milliseconds of operation, and increasing the size of Rs does not fix the problem, the
only real solution is to find a different brand and/or style of crystal. There is no practical way to
compensate for a crystal that exhibits poor self-suppression of the first overtone and first har-
monic. Once again, if a particular crystal type and brand is prone to starting at overtones or har-
monics, just don’t use it. No amount of circuit design will ever compensate for a bad or poor
quality crystal.
Usually, it is impossible to observe oscillator operation with an oscilloscope connected to one of the os-
cillator pins. The oscilloscope adds 3-30 pF and 1-10 M
of loading to V
SS, which will usually affect
oscillator operation. When the oscilloscope is connected to the EXTAL input, the 10 M
to V
SS (oscil-
loscope input) forms a resistive divider with Rf and often disables the oscillator by biasing the circuit out
of the linear region of the EXTAL input. This problem can sometimes be overcome by capacitively cou-
pling the oscilloscope with a very small capacitor (1-5 pF) between the oscilloscope probe and the os-
cillator pin.
It is better to observe the CLKOUT signal, since this does not alter the operation of the oscillator. It may
be possible to observe XTAL since it is isolated from the rest of the oscillator by Rs. Observe IDD without
the oscilloscope connected and again with it connected. If IDD is unchanged, it is usually safe to assume
the oscillator was unaffected. For additional information, see 2.5 Clock Circuitry.
5.2.4 Problem: System Crashes after Fetching Reset Vector
1. Incorrect reset configuration of boot memory width is causing the address bus to increment by
the wrong amount during fetches of the reset vectors. Check DATA0 to make sure that it is being
driven to the correct state during reset. If CSBOOT is a 16-bit port, drive DATA0 high during re-
set; if it is an 8-bit port, drive DATA0 low. See 2.1 Using Data Bus Pins to Configure the MCU.
2. An IRQ7 interrupt is received during or immediately after reset. The MCU will recognize the in-
terrupt after fetching the reset information and first instruction. In a typical system that is booting
out of ROM, stack RAM will not be enabled at this point, and the first bus cycle to write the stack
frame will hang the MCU. Make sure that the IRQ[7:1] lines are either pulled up through resistors
to 5 volts or configure the pins as PORTF I/O lines by pulling DATA9 low during reset. Also, start-
up software should enable the stack RAM (by configuring the appropriate chip-select circuits) be-
fore enabling the interrupt lines (by writing to the PFPAR register). This problem is likely to be
intermittent, as it would only occur if an IRQ7 interrupt is received in the short time before system
initialization. See 2.1 Using Data Bus Pins to Configure the MCU.
3. An interrupt is received, and the interrupt vectors have not been initialized. Make sure that the
interrupt vectors are initialized. See 4.1.3.2 Initializing Exception Vectors Other Than Reset.
4. The BR or BGACK pin has floated low and the CPU has relinquished control of the bus. Configure
these pins for chip-select operation out of reset by pulling DATA1 high during reset, or put pull-
up resistors on these pins.
5. Some of the pins are being powered up before VDD. If the MCU is connected to another system
with a separate power supply, use an LVI device to prevent the system with the faster power sup-
ply from driving logic one levels before the system with the slower power supply has become op-
erational. If this happens, the driven pins on the device with the slow supply will momentarily
have a higher voltage than the VDD pin. This condition can cause the input protection diodes to
become momentarily forward biased and cause significant current injection into the device sub-
strate, which will probably improperly charge or discharge some of the internal nodes of the
MCU. This action is completely random, and it is impossible to predict what will happen when
significant injection occurs. Usually, the MCU will not function at all and will display undefined
states. For example, the RESET, HALT, BERR, BR and FREEZE signals may be asserted but
the device may fail to fetch opcodes. See 2.7 Power Supply.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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