
MC68HC11KW1
MOTOROLA
4-7
OPERATING MODES AND ON-CHIP MEMORY
4
A/D result 3 (ADR3) high
$0044
(Bit 15)
(14)
(13)
(12)
(11)
(10)
(9)
(8)
undefined
A/D result 3 (ADR3) low
$0045
(7)
(6)
0
0
0
0
0
0
uu00 0000
A/D result 4 (ADR4) high
$0046 (Bit 15)
(14)
(13)
(12)
(11)
(10)
(9)
(8)
undefined
A/D result 4 (ADR4) low
$0047
(7)
(6)
0
0
0
0
0
0
uu00 0000
A/D result 5 (ADR5) high
$0048
(Bit 15)
(14)
(13)
(12)
(11)
(10)
(9)
(8)
undefined
A/D result 5 (ADR5) low
$0049
(7)
(6)
0
0
0
0
0
0
uu00 0000
A/D result 6 (ADR6) high
$004A (Bit 15)
(14)
(13)
(12)
(11)
(10)
(9)
(8)
undefined
A/D result 6 (ADR6) low
$004B
(7)
(6)
0
0
0
0
0
0
uu00 0000
A/D result 7 (ADR7) high
$004C
(Bit 15)
(14)
(13)
(12)
(11)
(10)
(9)
(8)
undefined
A/D result 7 (ADR7) low
$004D
(7)
(6)
0
0
0
0
0
0
uu00 0000
A/D result 8 (ADR8) high
$004E
(Bit 15)
(14)
(13)
(12)
(11)
(10)
(9)
(8)
undefined
A/D result 8 (ADR8) low
$004F
(7)
(6)
0
0
0
0
0
0
uu00 0000
Reserved
$0050
Reserved
$0051
Reserved
$0052
Reserved
$0053
Reserved
$0054
Reserved
$0055
Memory mapping window size
(MMSIZ)
$0056 MXGS2MXGS1W2SZ1 W2SZ0
0
0
W1SZ1 W1SZ0 0000 0000
Memory mapping window base (MMWBR)
$0057 W2A15 W2A14 W2A13
0
W1A15 W1A14 W1A13
0
0000 0000
Memory mapping window 1 control
(MM1CR)
$0058
0
X1A18 X1A17 X1A16 X1A15 X1A14 X1A13
0
0000 0000
Memory mapping window 2 control
(MM2CR)
$0059
0
X2A18 X2A17 X2A16 X2A15 X2A14 X2A13
0
0000 0000
Chip select clock stretch (CSCSTR)
$005A
IOSA
IOSB GP1SA GP1SB GP2SA GP2SB PCSA PCSB 0000 000x
Chip select control (CSCTL)
$005B
IOEN
IOPL IOCSA IOSZ GCSPRPCSENPCSZA PCSZB 0000 0100
Gen. purpose chip select 1 addr. (GPCS1A)
$005C G1A18 G1A17 G1A16 G1A15 G1A14 G1A13 G1A12 G1A11 0000 0000
Gen. purpose chip select 1 con. (GPCS1C)
$005D G1DG2G1DPC G1POL G1AV G1SZA G1SZB G1SZC G1SZD 0000 0000
Gen. purpose chip select 2 addr. (GPCS2A)
$005E
G2A18 G2A17 G2A16 G2A15 G2A14 G2A13 G2A12 G2A11 0000 0000
Gen. purpose chip select 2 con. (GPCS2C)
$005F
0
G2DPC G2POL G2AV G2SZA G2SZB G2SZC G2SZD 0000 0000
Pulse width clock select (PWCLK)
$0060 CON34 CON12 PCKA2 PCKA1
0
PCKB3 PCKB2 PCKB1 0000 0000
Pulse width polarity select (PWPOL)
$0061 PCLK4 PCLK3 PCLK2 PCLK1 PPOL4 PPOL3 PPOL2 PPOL1 0000 0000
Pulse width scale (PWSCAL)
$0062
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 0000 0000
Pulse width enable (PWEN)
$0063 TPWSL DISCP
0
0
PWEN4PWEN3PWEN2PWEN1 0000 0000
Pulse width count 1 (PWCNT1)
$0064
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 0000 0000
Table 4-2
Register and control bit assignments (Page 3 of 5)
Register name
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
TPG
49